Searched refs:PLL_ENABLE (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/phy/ti/ |
| H A D | phy-am654-serdes.c | 187 PLL_ENABLE, enumerator
228 [PLL_ENABLE] = REG_FIELD(WIZ_PLL_CTRL, 29, 31),
250 ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_ENABLE_STATE); in serdes_am654_enable_pll()
263 ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_DISABLE_STATE); in serdes_am654_disable_pll()
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| /linux/drivers/clk/spear/ |
| H A D | clk-vco-pll.c | 47 #define PLL_ENABLE 2 macro
317 parent_name, 0, mode_reg, PLL_ENABLE, 0, lock); in clk_register_vco_pll()
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| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra210.c | 322 #define PLL_ENABLE (1 << 30) macro
785 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) { in tegra210_pllcx_set_defaults()
838 if (val & PLL_ENABLE) { in tegra210_plla_set_defaults()
891 PLL_ENABLE) { in tegra210_plld_set_defaults()
944 if (val & PLL_ENABLE) { in plldss_defaults()
1063 if (val & PLL_ENABLE) { in tegra210_pllre_set_defaults()
1188 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { in tegra210_pllx_set_defaults()
1241 if (val & PLL_ENABLE) { in tegra210_pllmb_set_defaults()
1302 if (val & PLL_ENABLE) { in tegra210_pllp_set_defaults()
1365 if (val & PLL_ENABLE) { in tegra210_pllu_set_defaults()
[all …]
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| /linux/sound/soc/codecs/ |
| H A D | tlv320aic3x.h | 223 #define PLL_ENABLE 0x80 macro
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| /linux/drivers/clk/imx/ |
| H A D | clk-imx6q.c | 389 #define PLL_ENABLE BIT(13) macro
417 reg &= ~PLL_ENABLE; in disable_anatop_clocks()
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