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Searched refs:PLL_DIV (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/clk/x86/
H A Dclk-lgm.c114 #define PLL_DIV(x) ((x) + 0x04) macro
195 LGM_DIV(LGM_CLK_PP_HW, "pp_hw", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
197 LGM_DIV(LGM_CLK_PP_UC, "pp_uc", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
199 LGM_DIV(LGM_CLK_PP_FXD, "pp_fxd", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
201 LGM_DIV(LGM_CLK_PP_TBM, "pp_tbm", "pllpp", 0, PLL_DIV(CGU_PLLPP_CFG0),
204 PLL_DIV(CGU_PLL2_CFG0), 0, PLL_DIV_WIDTH, 24, 1, 0, 0,
206 LGM_DIV(LGM_CLK_CM, "cpu_cm", "pll0cz", 0, PLL_DIV(CGU_PLL0CZ_CFG0),
210 PLL_DIV(CGU_PLL0CZ_CFG0), 4, PLL_DIV_WIDTH, 25,
213 LGM_DIV(LGM_CLK_SDXC3, "sdxc3", "pll0cz", 0, PLL_DIV(CGU_PLL0CZ_CFG0),
217 CLK_IGNORE_UNUSED, PLL_DIV(CGU_PLL0CM0_CFG0),
[all …]
/linux/drivers/clk/at91/
H A Dclk-pll.c19 #define PLL_DIV(reg) ((reg) & PLL_DIV_MASK) macro
72 div = PLL_DIV(pllr); in clk_pll_prepare()
290 calc_rate = (pll->pms.parent_rate / PLL_DIV(pllr)) * in clk_pll_restore_context()
345 pll->div = PLL_DIV(pllr); in at91_clk_register_pll()
/linux/drivers/clk/
H A Dclk-sparx5.c19 #define PLL_DIV GENMASK(7, 0) macro
179 val |= FIELD_PREP(PLL_DIV, conf.div); in s5_pll_set_rate()
202 conf.div = FIELD_GET(PLL_DIV, val); in s5_pll_recalc_rate()