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Searched refs:PLL_35XX_RATE (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/clk/samsung/
H A Dclk-exynos5420.c1403 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1404 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1405 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1406 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1407 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1408 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1409 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1410 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1411 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
1412 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
[all …]
H A Dclk-exynos5260.c38 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
39 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
40 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
41 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
42 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
43 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
44 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
45 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
46 PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1),
47 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
[all …]
H A Dclk-exynos5250.c717 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
718 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
719 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
720 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
721 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
722 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
723 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
724 PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
725 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
726 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
[all …]
H A Dclk-exynos3250.c675 PLL_35XX_RATE(24 * MHZ, 1200000000, 400, 4, 1),
676 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
677 PLL_35XX_RATE(24 * MHZ, 1066000000, 533, 6, 1),
678 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
679 PLL_35XX_RATE(24 * MHZ, 960000000, 320, 4, 1),
680 PLL_35XX_RATE(24 * MHZ, 900000000, 300, 4, 1),
681 PLL_35XX_RATE(24 * MHZ, 850000000, 425, 6, 1),
682 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
683 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
684 PLL_35XX_RATE(24 * MHZ, 667000000, 667, 12, 1),
[all …]
H A Dclk-exynos5433.c738 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
739 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
740 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
741 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
742 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
743 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
744 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
745 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
746 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
747 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
[all …]
H A Dclk-exynos4.c1109 PLL_35XX_RATE(24 * MHZ, 1704000000, 213, 3, 0),
1110 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1111 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1112 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1113 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1114 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 4, 0),
1115 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 6, 0),
1116 PLL_35XX_RATE(24 * MHZ, 1000000000, 125, 3, 0),
1117 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 4, 0),
1118 PLL_35XX_RATE(24 * MHZ, 800000000, 100, 3, 0),
[all …]
H A Dclk-exynos850.c1159 PLL_35XX_RATE(26 * MHZ, 2210000000U, 255, 3, 0),
1160 PLL_35XX_RATE(26 * MHZ, 2106000000U, 243, 3, 0),
1161 PLL_35XX_RATE(26 * MHZ, 2002000000U, 231, 3, 0),
1162 PLL_35XX_RATE(26 * MHZ, 1846000000U, 213, 3, 0),
1163 PLL_35XX_RATE(26 * MHZ, 1742000000U, 201, 3, 0),
1164 PLL_35XX_RATE(26 * MHZ, 1586000000U, 183, 3, 0),
1165 PLL_35XX_RATE(26 * MHZ, 1456000000U, 168, 3, 0),
1166 PLL_35XX_RATE(26 * MHZ, 1300000000U, 150, 3, 0),
1167 PLL_35XX_RATE(26 * MHZ, 1157000000U, 267, 3, 1),
1168 PLL_35XX_RATE(26 * MHZ, 1053000000U, 243, 3, 1),
[all …]
H A Dclk-fsd.c149 PLL_35XX_RATE(24 * MHZ, 2000000000U, 250, 3, 0),
153 PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0),
157 PLL_35XX_RATE(24 * MHZ, 2400000000U, 200, 2, 0),
161 PLL_35XX_RATE(24 * MHZ, 1800000000U, 150, 2, 0),
1476 PLL_35XX_RATE(24 * MHZ, 666000000U, 111, 4, 0),
1636 PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 12, 0),
H A Dclk-pll.h53 #define PLL_35XX_RATE(_fin, _rate, _m, _p, _s) \ macro
H A Dclk-exynos7885.c732 PLL_35XX_RATE(26 * MHZ, 50000000U, 400, 13, 4),
H A Dclk-gs101.c2148 PLL_35XX_RATE(24576000, 19200000, 150, 6, 5),