Searched refs:PLLD_BASE (Results 1 – 2 of 2) sorted by relevance
50 #define PLLD_BASE 0xd0 macro627 .base_reg = PLLD_BASE,1500 plld_base = readl(clk_base + PLLD_BASE); in tegra124_132_clock_init_pre()1502 writel(plld_base, clk_base + PLLD_BASE); in tegra124_132_clock_init_pre()
71 #define PLLD_BASE 0xd0 macro647 csi_src = readl_relaxed(clk_base + PLLD_BASE); in tegra210_venc_mbist_war()648 writel_relaxed(csi_src | PLLD_BASE_CSI_CLKSOURCE, clk_base + PLLD_BASE); in tegra210_venc_mbist_war()659 writel_relaxed(csi_src, clk_base + PLLD_BASE); in tegra210_venc_mbist_war()2167 .base_reg = PLLD_BASE,3132 CLK_SET_RATE_PARENT, clk_base + PLLD_BASE, in tegra210_periph_clk_init()3801 value = readl(clk_base + PLLD_BASE); in tegra210_clock_init()3803 writel(value, clk_base + PLLD_BASE); in tegra210_clock_init()