Searched refs:PLLCA55 (Results 1 – 7 of 7) sorted by relevance
| /linux/drivers/clk/renesas/ |
| H A D | rzv2h-cpg.h | 39 #define PLLCA55 PLL_PACK(0x60, 1, 0) macro
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| H A D | r9a09g056-cpg.c | 161 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
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| H A D | r9a09g047-cpg.c | 128 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
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| H A D | r9a09g057-cpg.c | 165 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
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| /linux/arch/arm64/boot/dts/renesas/ |
| H A D | r9a09g056.dtsi | 43 * The default cluster table is based on the assumption that the PLLCA55 clock
44 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
47 * DTS based on the PLLCA55 clock frequency.
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| H A D | r9a09g047.dtsi | 25 * The default cluster table is based on the assumption that the PLLCA55 clock
26 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
29 * DTS based on the PLLCA55 clock frequency.
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| H A D | r9a09g057.dtsi | 25 * The default cluster table is based on the assumption that the PLLCA55 clock
26 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to
29 * DTS based on the PLLCA55 clock frequency.
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