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Searched refs:PIPE_CONTROL_QW_WRITE (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c79 *cs++ = PIPE_CONTROL_QW_WRITE; in gen6_emit_post_sync_nonzero_flush()
127 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; in gen6_emit_flush_rcs()
152 *cs++ = PIPE_CONTROL_QW_WRITE; in gen6_emit_breadcrumb_rcs()
163 PIPE_CONTROL_QW_WRITE | in gen6_emit_breadcrumb_rcs()
309 flags |= PIPE_CONTROL_QW_WRITE; in gen7_emit_flush_rcs()
360 PIPE_CONTROL_QW_WRITE | in gen7_emit_breadcrumb_rcs()
H A Dgen8_engine_cs.c35 flags |= PIPE_CONTROL_QW_WRITE; in gen8_emit_flush_rcs()
125 flags |= PIPE_CONTROL_QW_WRITE; in gen11_emit_flush_rcs()
149 flags |= PIPE_CONTROL_QW_WRITE; in gen11_emit_flush_rcs()
291 bit_group_1 |= PIPE_CONTROL_QW_WRITE; in gen12_emit_flush_rcs()
327 flags |= PIPE_CONTROL_QW_WRITE; in gen12_emit_flush_rcs()
H A Dgen2_engine_cs.c104 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; in gen4_emit_flush_rcs()
114 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; in gen4_emit_flush_rcs()
H A Dgen8_engine_cs.h82 *cs++ = flags1 | PIPE_CONTROL_QW_WRITE; in __gen8_emit_write_rcs()
H A Dintel_gpu_commands.h301 #define PIPE_CONTROL_QW_WRITE (1<<14) macro
H A Dintel_lrc.c1692 PIPE_CONTROL_QW_WRITE, in gen8_init_indirectctx_bb()
1764 PIPE_CONTROL_QW_WRITE, in gen9_init_indirectctx_bb()
/linux/drivers/gpu/drm/xe/instructions/
H A Dxe_gpu_commands.h56 #define PIPE_CONTROL_QW_WRITE (1<<14) macro
/linux/drivers/gpu/drm/xe/
H A Dxe_ring_ops.c151 PIPE_CONTROL_QW_WRITE | in emit_pipe_invalidate()
214 PIPE_CONTROL_QW_WRITE; in emit_pipe_imm_ggtt()