| /linux/drivers/phy/broadcom/ |
| H A D | phy-bcm-sr-usb.c | 21 PHY_CTRL, enumerator
29 [PHY_CTRL] = 0x14,
34 [PHY_CTRL] = 0x10,
39 [PHY_CTRL] = 0xc,
134 rd_data = readl(regs + offset[PHY_CTRL]); in bcm_usb_ss_phy_init()
137 writel(rd_data, regs + offset[PHY_CTRL]); in bcm_usb_ss_phy_init()
183 bcm_usb_reg32_clrbits(regs + offset[PHY_CTRL], in bcm_usb_phy_reset()
185 bcm_usb_reg32_setbits(regs + offset[PHY_CTRL], in bcm_usb_phy_reset()
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| /linux/drivers/phy/renesas/ |
| H A D | phy-rcar-gen3-pcie.c | 16 #define PHY_CTRL 0x4000 /* R8A77980 only */ macro
48 rcar_gen3_phy_pcie_modify_reg(p, PHY_CTRL, PHY_CTRL_PHY_PWDN, 0); in r8a77980_phy_pcie_power_on()
56 rcar_gen3_phy_pcie_modify_reg(p, PHY_CTRL, 0, PHY_CTRL_PHY_PWDN); in r8a77980_phy_pcie_power_off()
|
| /linux/drivers/phy/freescale/ |
| H A D | phy-fsl-imx8-mipi-dphy.c | 25 #define PHY_CTRL 0x00 macro
395 regmap_write(priv->lvds_regmap, PHY_CTRL, in mixel_dphy_configure_lvds_phy()
545 regmap_update_bits(priv->lvds_regmap, PHY_CTRL, LVDS_EN, LVDS_EN); in mixel_dphy_power_on_lvds_phy()
602 regmap_update_bits(priv->lvds_regmap, PHY_CTRL, LVDS_EN, 0); in mixel_dphy_power_off()
|
| /linux/drivers/mmc/host/ |
| H A D | sdhci-pci-arasan.c | 44 #define PHY_CTRL 0x24 macro
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| /linux/drivers/net/ethernet/intel/e1000/ |
| H A D | e1000_main.c | 419 e1000_read_phy_reg(hw, PHY_CTRL, &mii_reg); in e1000_power_up_phy()
421 e1000_write_phy_reg(hw, PHY_CTRL, mii_reg); in e1000_power_up_phy()
456 e1000_read_phy_reg(hw, PHY_CTRL, &mii_reg); in e1000_power_down_phy()
458 e1000_write_phy_reg(hw, PHY_CTRL, mii_reg); in e1000_power_down_phy()
4711 !e1000_read_phy_reg(hw, PHY_CTRL, in e1000_smartspeed()
4715 e1000_write_phy_reg(hw, PHY_CTRL, in e1000_smartspeed()
4726 !e1000_read_phy_reg(hw, PHY_CTRL, &phy_ctrl)) { in e1000_smartspeed()
4729 e1000_write_phy_reg(hw, PHY_CTRL, phy_ctrl); in e1000_smartspeed()
4800 case PHY_CTRL: in e1000_mii_ioctl()
4835 case PHY_CTRL: in e1000_mii_ioctl()
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| H A D | e1000_hw.h | 2478 #define PHY_CTRL 0x00 /* Control Register */ macro
|
| /linux/drivers/scsi/hisi_sas/ |
| H A D | hisi_sas_v1_hw.c | 126 #define PHY_CTRL (PORT_BASE + 0x14) macro
566 u32 phy_ctrl = hisi_sas_phy_read32(hisi_hba, i, PHY_CTRL); in reset_hw_v1_hw()
569 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, phy_ctrl); in reset_hw_v1_hw()
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| /linux/drivers/mtd/nand/raw/ |
| H A D | cadence-nand-controller.c | 289 #define PHY_CTRL 0x2080 macro
1381 writel_relaxed(t->phy_ctrl, cdns_ctrl->reg + PHY_CTRL); in cadence_nand_set_timings()
2852 writel_relaxed(t->phy_ctrl, cdns_ctrl->reg + PHY_CTRL); in cadence_nand_setup_nvddr_interface()
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| /linux/drivers/net/ethernet/intel/e1000e/ |
| H A D | phy.c | 2694 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) in e1000_access_phy_wakeup_reg_bm()
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| /linux/drivers/media/i2c/ccs/ |
| H A D | ccs-core.c | 1642 return ccs_write(sensor, PHY_CTRL, val); in ccs_update_phy_ctrl()
|