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Searched refs:PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_sh_mask.h4172 #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2 macro
H A Ddce_10_0_sh_mask.h4058 #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2 macro
H A Ddce_11_2_sh_mask.h4616 #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT 0x2 macro
H A Ddce_12_0_sh_mask.h10564 #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h20064 #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT … macro
H A Ddcn_3_0_3_sh_mask.h21890 #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT … macro
H A Ddcn_1_0_sh_mask.h41176 #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h36710 #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h43976 #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h43291 #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h49523 #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h49944 #define PHY_AUX_CNTL__AUXSLAVE_PAD_RXSEL__SHIFT … macro