Searched refs:PHYCLKPerState (Results 1 – 5 of 5) sorted by relevance
250 double PHYCLKPerState,
2088 mode_lib->vba.PHYCLKPerState[i], in dml32_ModeSupportAndSystemConfigurationFull()
603 double PHYCLKPerState[DC__VOLTAGE_STATES]; member
398 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()
75 dml_float_t PHYCLKPerState,5359 dml_float_t PHYCLKPerState, in CalculateOutputLink() argument5401 …*OutBpp = TruncToValidBPP(dml_min(600, PHYCLKPerState) * 10, 3, HTotal, HActive, PixelClockBackEnd… in CalculateOutputLink()5468 …putLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_hbr) && PHYCLKPerState >= 270) { in CalculateOutputLink()5471 …if (*OutBpp == 0 && PHYCLKPerState < 540 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutp… in CalculateOutputLink()5484 …dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_hbr2) && *OutBpp == 0 && PHYCLKPerState >= 540) { in CalculateOutputLink()5488 …if (*OutBpp == 0 && PHYCLKPerState < 810 && DSCEnable == dml_dsc_enable_if_necessary && ForcedOutp… in CalculateOutputLink()5501 …_rate_na || OutputLinkDPRate == dml_dp_rate_hbr3) && *OutBpp == 0 && PHYCLKPerState >= 810) { // V… in CalculateOutputLink()