Searched refs:PHYCLKD18PerState (Results 1 – 8 of 8) sorted by relevance
251 double PHYCLKD18PerState,
1338 double PHYCLKD18PerState, in dml32_CalculateOutputLink() argument
2089 mode_lib->vba.PHYCLKD18PerState[i], in dml32_ModeSupportAndSystemConfigurationFull()
1088 double PHYCLKD18PerState[DC__VOLTAGE_STATES]; member
399 mode_lib->vba.PHYCLKD18PerState[i] = soc->clock_limits[i].phyclk_d18_mhz; in fetch_socbb_params()
4419 v->PHYCLKD18PerState[k] >= 10000.0 / 18.0) {4435 if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 13500.0 / 18.0 &&4461 v->PHYCLKD18PerState[k] >= 13500.0 / 18.0) {4477 if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 20000.0 / 18.0 &&4503 v->PHYCLKD18PerState[k] >= 20000.0 / 18.0) {
4332 v->PHYCLKD18PerState[k] >= 10000.0 / 18.0) {4348 if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 13500.0 / 18.0 &&4374 v->PHYCLKD18PerState[k] >= 13500.0 / 18.0) {4390 if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 20000.0 / 18.0 &&4416 v->PHYCLKD18PerState[k] >= 20000.0 / 18.0) {
75 dml_float_t PHYCLKD18PerState,5341 dml_float_t PHYCLKD18PerState, in CalculateOutputLink() argument