Searched refs:PHYCLKD18PerState (Results 1 – 5 of 5) sorted by relevance
251 double PHYCLKD18PerState,
2089 mode_lib->vba.PHYCLKD18PerState[i], in dml32_ModeSupportAndSystemConfigurationFull()
1088 double PHYCLKD18PerState[DC__VOLTAGE_STATES]; member
399 mode_lib->vba.PHYCLKD18PerState[i] = soc->clock_limits[i].phyclk_d18_mhz; in fetch_socbb_params()
4329 v->PHYCLKD18PerState[k] >= 10000.0 / 18.0) {4345 if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 13500.0 / 18.0 &&4371 v->PHYCLKD18PerState[k] >= 13500.0 / 18.0) {4387 if (v->Outbpp == BPP_INVALID && v->PHYCLKD18PerState[k] < 20000.0 / 18.0 &&4413 v->PHYCLKD18PerState[k] >= 20000.0 / 18.0) {