| /linux/include/dt-bindings/clock/ |
| H A D | samsung,s3c64xx-clock.h | 84 #define PCLK_WDT 69 macro
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| H A D | rk3036-cru.h | 77 #define PCLK_WDT 368 macro
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| H A D | exynos7-clk.h | 125 #define PCLK_WDT 3 macro
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| H A D | rk3188-cru-common.h | 83 #define PCLK_WDT 331 macro
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| H A D | rk3128-cru.h | 92 #define PCLK_WDT 319 macro
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| H A D | rv1108-cru.h | 135 #define PCLK_WDT 284 macro
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| H A D | rk3308-cru.h | 193 #define PCLK_WDT 214 macro
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| H A D | rk3368-cru.h | 150 #define PCLK_WDT 368 macro
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| H A D | rk3288-cru.h | 160 #define PCLK_WDT 368 macro
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| H A D | rk3328-cru.h | 167 #define PCLK_WDT 236 macro
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| H A D | rockchip,rv1126-cru.h | 310 #define PCLK_WDT 248 macro
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| H A D | rk3399-cru.h | 275 #define PCLK_WDT 380 macro
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| H A D | rockchip,rk3588-cru.h | 233 #define PCLK_WDT 218 macro
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| /linux/drivers/clk/samsung/ |
| H A D | clk-s3c64xx.c | 240 GATE_BUS(PCLK_WDT, "pclk_wdt", "pclk", PCLK_GATE, 5),
345 ALIAS(PCLK_WDT, NULL, "watchdog"),
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| H A D | clk-exynos7.c | 844 GATE(PCLK_WDT, "pclk_wdt", "mout_aclk_peris_66_user",
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| /linux/arch/arm/boot/dts/samsung/ |
| H A D | s3c64xx.dtsi | 101 clocks = <&clocks PCLK_WDT>;
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 416 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
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| H A D | clk-rk3128.c | 506 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
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| H A D | clk-rk3328.c | 796 SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_bus"),
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| H A D | clk-rv1108.c | 632 GATE(PCLK_WDT, "pclk_wdt", "pclk_bus_pre", 0,
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| H A D | clk-rk3188.c | 519 GATE(PCLK_WDT, "pclk_wdt", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 15, GFLAGS),
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| H A D | clk-rk3368.c | 817 SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),
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| H A D | clk-rk3288.c | 774 SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),
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| /linux/arch/arm/boot/dts/rockchip/ |
| H A D | rk3xxx.dtsi | 352 clocks = <&cru PCLK_WDT>;
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| /linux/arch/arm64/boot/dts/exynos/ |
| H A D | exynos7.dtsi | 556 clocks = <&clock_peris PCLK_WDT>;
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