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Searched refs:PCLK_CSIPHY0 (Results 1 – 7 of 7) sorted by relevance

/linux/include/dt-bindings/clock/
H A Drockchip,rv1126b-cru.h198 #define PCLK_CSIPHY0 185 macro
H A Drockchip,rv1126-cru.h350 #define PCLK_CSIPHY0 290 macro
H A Drockchip,rk3588-cru.h269 #define PCLK_CSIPHY0 254 macro
/linux/drivers/clk/rockchip/
H A Dclk-rv1126.c894 GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_pdtop", 0,
H A Dclk-rv1126b.c655 GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_vi_root", 0,
H A Dclk-rk3588.c789 GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0,
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3588-base.dtsi3193 clocks = <&cru PCLK_CSIPHY0>;