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Searched refs:PCLK (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/clk/stm32/
H A Dclk-stm32mp1.c1383 #define PCLK(_id, _name, _parent, _flags, _mgate)\ macro
1887 PCLK(TIM2, "tim2", "pclk1", CLK_IGNORE_UNUSED, G_TIM2),
1888 PCLK(TIM3, "tim3", "pclk1", CLK_IGNORE_UNUSED, G_TIM3),
1889 PCLK(TIM4, "tim4", "pclk1", CLK_IGNORE_UNUSED, G_TIM4),
1890 PCLK(TIM5, "tim5", "pclk1", CLK_IGNORE_UNUSED, G_TIM5),
1891 PCLK(TIM6, "tim6", "pclk1", CLK_IGNORE_UNUSED, G_TIM6),
1892 PCLK(TIM7, "tim7", "pclk1", CLK_IGNORE_UNUSED, G_TIM7),
1893 PCLK(TIM12, "tim12", "pclk1", CLK_IGNORE_UNUSED, G_TIM12),
1894 PCLK(TIM13, "tim13", "pclk1", CLK_IGNORE_UNUSED, G_TIM13),
1895 PCLK(TIM14, "tim14", "pclk1", CLK_IGNORE_UNUSED, G_TIM14),
[all …]
/linux/arch/arm/boot/dts/gemini/
H A Dgemini.dtsi163 clock-names = "PCLK";
187 clock-names = "PCLK", "EXTCLK";
197 clock-names = "PCLK", "EXTCLK";
284 clock-names = "PCLK", "PCICLK";
362 clock-names = "PCLK";
373 clock-names = "PCLK";
391 clock-names = "PCLK";
404 clock-names = "PCLK";
435 clock-names = "PCLK", "TVE";
447 clock-names = "PCLK";
[all …]
/linux/sound/soc/meson/
H A Daiu.c86 return clk_prepare_enable(aiu->i2s.clks[PCLK].clk); in aiu_cpu_component_probe()
93 clk_disable_unprepare(aiu->i2s.clks[PCLK].clk); in aiu_cpu_component_remove()
200 [PCLK] = "i2s_pclk",
207 [PCLK] = "spdif_pclk",
H A Daiu.h18 PCLK = 0, enumerator
H A Daiu-fifo-spdif.c184 fifo->pclk = aiu->spdif.clks[PCLK].clk; in aiu_fifo_spdif_dai_probe()
H A Daiu-fifo-i2s.c169 fifo->pclk = aiu->i2s.clks[PCLK].clk; in aiu_fifo_i2s_dai_probe()
/linux/Documentation/devicetree/bindings/timer/
H A Dfaraday,fttmr010.txt23 - clock-names : should be "EXTCLK" and "PCLK" for the external tick timer
37 clock-names = "EXTCLK", "PCLK";
/linux/Documentation/admin-guide/media/
H A Dmgb4.rst142 Width of the HSYNC signal in PCLK clock ticks.
148 Width of the VSYNC signal in PCLK clock ticks.
154 Number of PCLK pulses between deassertion of the HSYNC signal and the first
161 Number of PCLK pulses between the end of the last valid pixel in the video
183 derived from the Pixel Clock Frequency (PCLK) and is equal to PCLK if
184 oldi_lane_width is set to "single" and PCLK/2 if oldi_lane_width is set to
273 Number of PCLK pulses between deassertion of the HSYNC signal and the first
277 Number of PCLK pulses between the end of the last valid pixel in the video
/linux/arch/arm/boot/dts/moxa/
H A Dmoxart.dtsi65 clock-names = "PCLK";
93 clock-names = "PCLK";
/linux/drivers/clk/samsung/
H A Dclk-s3c64xx.c164 DIV(PCLK, "pclk", "hclkx2", CLK_DIV0, 12, 4),
318 ALIAS(PCLK, NULL, "pclk"),
319 ALIAS(PCLK, NULL, "clk_uart_baud2"),
/linux/include/dt-bindings/clock/
H A Dsamsung,s3c64xx-clock.h28 #define PCLK 9 macro
/linux/Documentation/devicetree/bindings/clock/
H A Dst,nomadik.txt36 lines from the PCLK clock tree.
/linux/Documentation/gpu/amdgpu/display/
H A Ddc-glossary.rst34 * PCLK: Pixel Clock
/linux/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi232 /* The PCLK domain uses HCLK right off */
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-g6.dtsi511 clock-names = "PCLK";
H A Daspeed-g4.dtsi294 clock-names = "PCLK";
H A Daspeed-g5.dtsi378 clock-names = "PCLK";
/linux/Documentation/fb/
H A Dmatroxfb.rst143 transaction terminate with success or retry in 32 PCLK).
/linux/Documentation/networking/device_drivers/hamradio/
H A Dz8530drv.rst109 pclock - the clock at the PCLK pin of the Z8530 (option, 4915200 is
/linux/arch/arm/boot/dts/ti/omap/
H A Dam437x-gp-evm.dts294 AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
/linux/drivers/watchdog/
H A DKconfig566 The driver is limited by the speed of the system's PCLK
567 signal, so with reasonably fast systems (PCLK around 50-66MHz)