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Searched refs:PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/pcie/
H A Dpcie_6_1_0_sh_mask.h384 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h7555 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x00000001 macro
H A Dbif_4_1_sh_mask.h2880 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 macro
H A Dbif_5_0_sh_mask.h10560 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 macro
H A Dbif_5_1_sh_mask.h3834 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT 0x1 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_4_sh_mask.h42350 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT … macro
H A Dnbio_4_3_0_sh_mask.h31261 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT … macro
H A Dnbio_2_3_sh_mask.h53487 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT … macro
H A Dnbio_6_1_sh_mask.h37725 #define PCIE_P_PORT_LANE_STATUS__PHY_LINK_WIDTH__SHIFT … macro