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Searched refs:PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v2_3.c362 data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; in nbio_v2_3_enable_aspm()
364 data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; in nbio_v2_3_enable_aspm()
481 data |= NAVI10_PCIE__LC_L1_INACTIVITY_TBT_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; in nbio_v2_3_program_aspm()
483 data |= NAVI10_PCIE__LC_L1_INACTIVITY_DEFAULT << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; in nbio_v2_3_program_aspm()
H A Dnbio_v6_1.c381 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; in nbio_v6_1_program_aspm()
H A Dnbif_v6_3_1.c424 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; in nbif_v6_3_1_program_aspm()
H A Dnbio_v4_3.c463 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT; in nbio_v4_3_program_aspm()
/linux/drivers/gpu/drm/amd/include/asic_reg/pcie/
H A Dpcie_6_1_0_sh_mask.h593 #define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h7055 #define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0x0000000c macro
H A Dbif_4_1_sh_mask.h3012 #define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc macro
H A Dbif_5_0_sh_mask.h10744 #define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc macro
H A Dbif_5_1_sh_mask.h3966 #define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT 0xc macro
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_4_sh_mask.h42565 #define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT … macro
H A Dnbio_4_3_0_sh_mask.h31460 #define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT … macro
H A Dnbio_2_3_sh_mask.h53708 #define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT … macro
H A Dnbio_6_1_sh_mask.h37925 #define PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT … macro