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Searched refs:PCIE_CNTL2__SLV_MEM_LS_EN_MASK (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v7_2.c271 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK; in nbio_v7_2_update_medium_grain_light_sleep()
273 data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK; in nbio_v7_2_update_medium_grain_light_sleep()
294 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in nbio_v7_2_update_medium_grain_light_sleep()
298 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in nbio_v7_2_update_medium_grain_light_sleep()
320 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) in nbio_v7_2_get_clockgating_state()
H A Dnbio_v7_0.c194 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in nbio_v7_0_update_medium_grain_light_sleep()
198 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in nbio_v7_0_update_medium_grain_light_sleep()
219 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) in nbio_v7_0_get_clockgating_state()
H A Dnbio_v6_1.c199 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in nbio_v6_1_update_medium_grain_light_sleep()
203 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in nbio_v6_1_update_medium_grain_light_sleep()
224 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) in nbio_v6_1_get_clockgating_state()
H A Dnbio_v2_3.c268 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in nbio_v2_3_update_medium_grain_light_sleep()
272 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in nbio_v2_3_update_medium_grain_light_sleep()
293 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) in nbio_v2_3_get_clockgating_state()
H A Dnbio_v4_3.c279 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK; in nbio_v4_3_update_medium_grain_light_sleep()
281 data &= ~PCIE_CNTL2__SLV_MEM_LS_EN_MASK; in nbio_v4_3_update_medium_grain_light_sleep()
300 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) in nbio_v4_3_get_clockgating_state()
/linux/drivers/gpu/drm/amd/include/asic_reg/pcie/
H A Dpcie_6_1_0_sh_mask.h2456 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK … macro
/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h6646 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L macro
H A Dbif_4_1_sh_mask.h2059 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 macro
H A Dbif_5_0_sh_mask.h2631 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 macro
H A Dbif_5_1_sh_mask.h3013 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_4_sh_mask.h43498 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK … macro
H A Dnbio_4_3_0_sh_mask.h32779 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK … macro
H A Dnbio_7_0_sh_mask.h74167 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK … macro
H A Dnbio_2_3_sh_mask.h54853 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK … macro
H A Dnbio_6_1_sh_mask.h38794 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK … macro
H A Dnbio_7_2_0_sh_mask.h100188 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK … macro