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Searched refs:PA_CL_UCP_1_Z__DATA_REGISTER_MASK (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h5623 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff macro
H A Dgfx_8_1_sh_mask.h6945 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff macro
H A Dgfx_8_0_sh_mask.h6411 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK 0xffffffff macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h15482 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK … macro
H A Dgc_9_1_sh_mask.h16787 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK … macro
H A Dgc_9_2_1_sh_mask.h16659 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK … macro
H A Dgc_9_4_2_sh_mask.h8908 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK … macro
H A Dgc_11_5_0_sh_mask.h16545 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK … macro
H A Dgc_11_0_0_sh_mask.h20576 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK … macro
H A Dgc_12_0_0_sh_mask.h28249 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK … macro
H A Dgc_10_1_0_sh_mask.h22980 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK … macro
H A Dgc_11_0_3_sh_mask.h22906 #define PA_CL_UCP_1_Z__DATA_REGISTER_MASK … macro