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Searched refs:PA_CL_CLIP_CNTL__UCP_ENA_5_MASK (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h5575 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20 macro
H A Dgfx_8_1_sh_mask.h6897 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20 macro
H A Dgfx_8_0_sh_mask.h6363 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK 0x20 macro
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h16917 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK … macro
H A Dgc_9_1_sh_mask.h18222 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK … macro
H A Dgc_9_2_1_sh_mask.h18098 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK … macro
H A Dgc_9_4_2_sh_mask.h10345 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK … macro
H A Dgc_11_5_0_sh_mask.h18091 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK … macro
H A Dgc_11_0_0_sh_mask.h22117 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK … macro
H A Dgc_12_0_0_sh_mask.h30214 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK … macro
H A Dgc_10_1_0_sh_mask.h24409 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK … macro
H A Dgc_11_0_3_sh_mask.h24447 #define PA_CL_CLIP_CNTL__UCP_ENA_5_MASK … macro