| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | dml2_utils.c | 127 dml_output_array->OutputLinkDPRate[dst_index] = dml_output_array->OutputLinkDPRate[src_index]; in dml2_util_copy_dml_output()
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| H A D | display_mode_core.c | 96 enum dml_output_link_dp_rate OutputLinkDPRate,
5410 enum dml_output_link_dp_rate OutputLinkDPRate, in CalculateOutputLink()
5458 if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_uhbr10) && PHYCLKD32PerState >= 10000 / 32.0) { in CalculateOutputLink()
5471 if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_uhbr13p5) && *OutBpp == 0 && PHYCLKD32PerState >= 13500 / 32.0) { in CalculateOutputLink()
5485 if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate == dml_dp_rate_uhbr20) && *OutBpp == 0 && PHYCLKD32PerState >= 20000 / 32) { in CalculateOutputLink()
5500 if ((OutputLinkDPRate == dml_dp_rate_na || OutputLinkDPRate in CalculateOutputLink()
5378 CalculateOutputLink(dml_float_t PHYCLKPerState,dml_float_t PHYCLKD18PerState,dml_float_t PHYCLKD32PerState,dml_float_t Downspreading,dml_bool_t IsMainSurfaceUsingTheIndicatedTiming,enum dml_output_encoder_class Output,enum dml_output_format_class OutputFormat,dml_uint_t HTotal,dml_uint_t HActive,dml_float_t PixelClockBackEnd,dml_float_t ForcedOutputLinkBPP,dml_uint_t DSCInputBitPerComponent,dml_uint_t NumberOfDSCSlices,dml_float_t AudioSampleRate,dml_uint_t AudioSampleLayout,enum dml_odm_mode ODMModeNoDSC,enum dml_odm_mode ODMModeDSC,enum dml_dsc_enable DSCEnable,dml_uint_t OutputLinkDPLanes,enum dml_output_link_dp_rate OutputLinkDPRate,dml_bool_t * RequiresDSC,dml_bool_t * RequiresFEC,dml_float_t * OutBpp,enum dml_output_type_and_rate__type * OutputType,enum dml_output_type_and_rate__rate * OutputRate,dml_uint_t * RequiredSlots) CalculateOutputLink() argument
[all...] |
| H A D | display_mode_core_structs.h | 629 enum dml_output_link_dp_rate OutputLinkDPRate[__DML_NUM_PLANES__]; member
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| H A D | dml2_translation_helper.c | 891 out->OutputLinkDPRate[location] = dml_dp_rate_na; in populate_dml_output_cfg_from_stream_state()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_util_32.h | 269 enum dm_output_link_dp_rate OutputLinkDPRate,
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| H A D | display_mode_vba_32.c | 2112 mode_lib->vba.OutputLinkDPRate[k], in dml32_ModeSupportAndSystemConfigurationFull()
2376 if (((mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr in dml32_ModeSupportAndSystemConfigurationFull()
2377 || mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr2 in dml32_ModeSupportAndSystemConfigurationFull()
2378 || mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_hbr3) in dml32_ModeSupportAndSystemConfigurationFull()
2380 || ((mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr10 in dml32_ModeSupportAndSystemConfigurationFull()
2381 || mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr13p5 in dml32_ModeSupportAndSystemConfigurationFull()
2382 || mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_uhbr20) in dml32_ModeSupportAndSystemConfigurationFull()
2388 && mode_lib->vba.OutputLinkDPRate[k] == dm_dp_rate_na) in dml32_ModeSupportAndSystemConfigurationFull()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.h | 651 enum dm_output_link_dp_rate OutputLinkDPRate[DC__NUM_DPP__MAX]; member
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| H A D | display_mode_vba.c | 571 mode_lib->vba.OutputLinkDPRate[mode_lib->vba.NumberOfActivePlanes] = dout->dp_rate; in fetch_pipe_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_dcn4_calcs.c | 4270 enum dml2_output_link_dp_rate OutputLinkDPRate, in CalculateOutputLink()
4300 DML_LOG_VERBOSE("DML::%s: OutputLinkDPRate = %u\n", __func__, OutputLinkDPRate); in CalculateOutputLink()
4330 if ((OutputLinkDPRate == dml2_dp_rate_na || OutputLinkDPRate == dml2_dp_rate_uhbr10) && PHYCLKD32 >= 10000.0 / 32) { in CalculateOutputLink()
4343 if ((OutputLinkDPRate == dml2_dp_rate_na || OutputLinkDPRate == dml2_dp_rate_uhbr13p5) && *OutBpp == 0 && PHYCLKD32 >= 13500.0 / 32) { in CalculateOutputLink()
4357 if ((OutputLinkDPRate == dml2_dp_rate_na || OutputLinkDPRate == dml2_dp_rate_uhbr20) && *OutBpp == 0 && PHYCLKD32 >= 20000.0 / 32) { in CalculateOutputLink()
4372 if ((OutputLinkDPRate in CalculateOutputLink()
4243 CalculateOutputLink(struct dml2_core_internal_scratch * s,double PHYCLK,double PHYCLKD18,double PHYCLKD32,double Downspreading,enum dml2_output_encoder_class Output,enum dml2_output_format_class OutputFormat,unsigned int HTotal,unsigned int HActive,double PixelClockBackEnd,double ForcedOutputLinkBPP,unsigned int DSCInputBitPerComponent,unsigned int NumberOfDSCSlices,double AudioSampleRate,unsigned int AudioSampleLayout,enum dml2_odm_mode ODMModeNoDSC,enum dml2_odm_mode ODMModeDSC,enum dml2_dsc_enable_option DSCEnable,unsigned int OutputLinkDPLanes,enum dml2_output_link_dp_rate OutputLinkDPRate,bool * RequiresDSC,bool * RequiresFEC,double * OutBpp,enum dml2_core_internal_output_type * OutputType,enum dml2_core_internal_output_type_rate * OutputRate,unsigned int * RequiredSlots) CalculateOutputLink() argument
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