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Searched refs:OTG_M_CONST_DTO0 (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c214 REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, 0); in optc3_fpu_set_vrr_m_const()
236 REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, 0); in optc3_fpu_set_vrr_m_const()
253 REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, (uint32_t)phase); in optc3_fpu_set_vrr_m_const()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/
H A Ddcn31_optc.h64 SRI(OTG_M_CONST_DTO0, OTG, inst),\
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/
H A Ddcn314_optc.h65 SRI(OTG_M_CONST_DTO0, OTG, inst),\
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.h252 SRI_ARR(OTG_M_CONST_DTO0, OTG, inst),\
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn30/
H A Ddcn30_optc.h69 SRI(OTG_M_CONST_DTO0, OTG, inst),\
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/
H A Ddcn10_optc.h190 uint32_t OTG_M_CONST_DTO0; member
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.h505 SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h1023 SRI_ARR(OTG_M_CONST_DTO0, OTG, inst), \