Searched refs:OTG_H_TOTAL (Results 1 – 11 of 11) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/ |
| H A D | dcn20_optc.c | 281 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total); in optc2_align_vblanks()
299 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total); in optc2_align_vblanks()
571 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn20_timing_generator_init()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/ |
| H A D | dcn10_optc.c | 192 REG_SET(OTG_H_TOTAL, 0, in optc1_program_timing()
193 OTG_H_TOTAL, patched_crtc_timing.h_total - 1); in optc1_program_timing()
1374 REG_GET(OTG_H_TOTAL, in optc1_read_otg_state()
1375 OTG_H_TOTAL, &s->h_total); in optc1_read_otg_state()
1672 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn10_timing_generator_init()
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| H A D | dcn10_optc.h | 42 SRI(OTG_H_TOTAL, OTG, inst),\
120 uint32_t OTG_H_TOTAL; member
231 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
382 type OTG_H_TOTAL;\
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/ |
| H A D | dcn201_optc.c | 189 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn201_timing_generator_init()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/ |
| H A D | dcn314_optc.c | 264 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn314_timing_generator_init()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/ |
| H A D | dcn31_optc.c | 315 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn31_timing_generator_init()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn401/ |
| H A D | dcn401_optc.h | 26 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\
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| H A D | dcn401_optc.c | 536 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn401_timing_generator_init()
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| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn35/ |
| H A D | dcn35_optc.c | 501 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; in dcn35_timing_generator_init()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.h | 228 SRI_ARR(OTG_H_TOTAL, OTG, inst),\
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.h | 1005 SRI_ARR(OTG_H_TOTAL, OTG, inst), \
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