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Searched refs:OTG_H_TIMING_CNTL (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/
H A Ddcn314_optc.c100 REG_UPDATE(OTG_H_TIMING_CNTL, in optc314_set_odm_combine()
178 REG_UPDATE(OTG_H_TIMING_CNTL, in optc314_set_odm_bypass()
190 REG_UPDATE(OTG_H_TIMING_CNTL, in optc314_set_h_timing_div_manual_mode()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn401/
H A Ddcn401_optc.c124 REG_UPDATE(OTG_H_TIMING_CNTL, in optc401_set_odm_combine()
143 REG_UPDATE(OTG_H_TIMING_CNTL, in optc401_set_odm_combine()
155 REG_UPDATE(OTG_H_TIMING_CNTL, in optc401_set_odm_combine()
169 REG_UPDATE(OTG_H_TIMING_CNTL, in optc401_set_h_timing_div_manual_mode()
277 REG_UPDATE(OTG_H_TIMING_CNTL, in optc401_set_odm_bypass()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn20/
H A Ddcn20_optc.c171 REG_WRITE(OTG_H_TIMING_CNTL, 0); in optc2_set_odm_bypass()
174 REG_UPDATE(OTG_H_TIMING_CNTL, in optc2_set_odm_bypass()
216 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_BY2, 1); in optc2_set_odm_combine()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/
H A Ddcn31_optc.c88 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc31_set_odm_combine()
240 REG_SET(OTG_H_TIMING_CNTL, 0, in optc3_init_odm()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/
H A Ddcn10_optc.h46 SRI(OTG_H_TIMING_CNTL, OTG, inst),\
124 uint32_t OTG_H_TIMING_CNTL; member
H A Ddcn10_optc.c323 REG_UPDATE(OTG_H_TIMING_CNTL, in optc1_program_timing()
326 REG_UPDATE(OTG_H_TIMING_CNTL, in optc1_program_timing()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn35/
H A Ddcn35_optc.c108 REG_UPDATE(OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); in optc35_set_odm_combine()
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.h232 SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst),\
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h1008 SRI_ARR(OTG_H_TIMING_CNTL, OTG, inst), SRI_ARR(OTG_V_TOTAL, OTG, inst), \