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Searched refs:OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h24226 #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h25699 #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h27052 #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h30165 #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT … macro
H A Ddcn_3_5_1_sh_mask.h23244 #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT … macro
H A Ddcn_3_5_0_sh_mask.h23265 #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h32002 #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h29938 #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h32766 #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h33890 #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h29087 #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h33504 #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h32634 #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h27076 #define OTG3_OTG_COUNT_CONTROL__OTG_HORZ_REPETITION_COUNT__SHIFT … macro