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Searched refs:OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h24146 #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h25634 #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h26987 #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h30084 #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_5_1_sh_mask.h23190 #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_5_0_sh_mask.h23211 #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h31937 #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h29873 #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h32701 #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h33825 #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h29022 #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h33422 #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h32569 #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h27011 #define OTG3_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro