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Searched refs:OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h23519 #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_0_1_sh_mask.h24982 #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_2_1_sh_mask.h26357 #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_2_1_0_sh_mask.h29438 #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_5_1_sh_mask.h22654 #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_5_0_sh_mask.h22675 #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_1_2_sh_mask.h31297 #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_1_5_sh_mask.h29233 #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_1_6_sh_mask.h32061 #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_1_4_sh_mask.h33195 #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_0_2_sh_mask.h28370 #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_2_0_0_sh_mask.h32779 #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_0_0_sh_mask.h31918 #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_2_0_sh_mask.h26381 #define OTG2_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro