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Searched refs:OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_sh_mask.h15288 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT macro
H A Ddcn_3_0_3_sh_mask.h15461 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT macro
H A Ddcn_1_0_sh_mask.h22695 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT macro
H A Ddcn_3_0_1_sh_mask.h24146 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT macro
H A Ddcn_3_2_1_sh_mask.h25545 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT macro
H A Ddcn_2_1_0_sh_mask.h28588 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT macro
H A Ddcn_3_5_1_sh_mask.h21959 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT macro
H A Ddcn_3_5_0_sh_mask.h21980 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT macro
H A Ddcn_3_1_2_sh_mask.h30473 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT macro
H A Ddcn_3_1_5_sh_mask.h28438 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT macro
H A Ddcn_3_1_6_sh_mask.h31237 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT macro
H A Ddcn_3_1_4_sh_mask.h32383 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT macro
H A Ddcn_3_0_2_sh_mask.h27534 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT macro
H A Ddcn_2_0_0_sh_mask.h31933 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT macro
H A Ddcn_3_0_0_sh_mask.h31083 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT macro
H A Ddcn_3_2_0_sh_mask.h25569 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING__SHIFT macro