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Searched refs:OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_sh_mask.h15300 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_0_3_sh_mask.h15471 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_1_0_sh_mask.h22705 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_0_1_sh_mask.h24156 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_2_1_sh_mask.h25554 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_2_1_0_sh_mask.h28600 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_5_1_sh_mask.h21968 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_5_0_sh_mask.h21989 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_1_2_sh_mask.h30483 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_1_5_sh_mask.h28448 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_1_6_sh_mask.h31247 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_1_4_sh_mask.h32392 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_0_2_sh_mask.h27544 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_2_0_0_sh_mask.h31945 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_0_0_sh_mask.h31093 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro
H A Ddcn_3_2_0_sh_mask.h25578 #define OTG1_OTG_DOUBLE_BUFFER_CONTROL__OTG_UPDATE_PENDING_MASK … macro