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Searched refs:OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_sh_mask.h15126 #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK … macro
H A Ddcn_3_0_3_sh_mask.h15306 #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK … macro
H A Ddcn_1_0_sh_mask.h22526 #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK … macro
H A Ddcn_3_0_1_sh_mask.h23991 #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK … macro
H A Ddcn_3_2_1_sh_mask.h25390 #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK … macro
H A Ddcn_2_1_0_sh_mask.h28419 #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK … macro
H A Ddcn_3_5_1_sh_mask.h21827 #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK … macro
H A Ddcn_3_5_0_sh_mask.h21848 #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK … macro
H A Ddcn_3_1_2_sh_mask.h30318 #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK … macro
H A Ddcn_3_1_5_sh_mask.h28312 #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK … macro
H A Ddcn_3_1_6_sh_mask.h31082 #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK … macro
H A Ddcn_3_1_4_sh_mask.h32228 #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK … macro
H A Ddcn_3_0_2_sh_mask.h27379 #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK … macro
H A Ddcn_2_0_0_sh_mask.h31766 #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK … macro
H A Ddcn_3_0_0_sh_mask.h30928 #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK … macro
H A Ddcn_3_2_0_sh_mask.h25414 #define OTG1_OTG_CONTROL__OTG_CURRENT_MASTER_EN_STATE_MASK … macro