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Searched refs:OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_1_sh_mask.h14339 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_0_3_sh_mask.h14471 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_1_0_sh_mask.h21704 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h23156 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h24578 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h27570 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_5_1_sh_mask.h21132 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_5_0_sh_mask.h21153 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h29495 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h27518 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h30259 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h31416 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h26544 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h30920 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h30094 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h24602 #define OTG0_OTG_CONTROL__OTG_FIELD_NUMBER_CNTL__SHIFT … macro