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Searched refs:ORION5X_BRIDGE_VIRT_BASE (Results 1 – 3 of 3) sorted by relevance

/linux/arch/arm/mach-orion5x/
H A Dbridge-regs.h9 #define CPU_CONF (ORION5X_BRIDGE_VIRT_BASE + 0x100)
11 #define CPU_CTRL (ORION5X_BRIDGE_VIRT_BASE + 0x104)
13 #define RSTOUTn_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x108)
16 #define CPU_SOFT_RESET (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
18 #define BRIDGE_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x110)
20 #define POWER_MNG_CTRL_REG (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
24 #define MAIN_IRQ_CAUSE (ORION5X_BRIDGE_VIRT_BASE + 0x200)
26 #define MAIN_IRQ_MASK (ORION5X_BRIDGE_VIRT_BASE + 0x204)
28 #define TIMER_VIRT_BASE (ORION5X_BRIDGE_VIRT_BASE + 0x300)
H A Dorion5x.h81 #define ORION5X_BRIDGE_VIRT_BASE (ORION5X_REGS_VIRT_BASE + 0x20000) macro
H A Dcommon.c263 orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR, in orion5x_timer_init()