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Searched refs:OMAP1_IO_ADDRESS (Results 1 – 9 of 9) sorted by relevance

/linux/arch/arm/mach-omap1/
H A Dclock_data.c99 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
109 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
130 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
147 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
157 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
169 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
180 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
200 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
270 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
277 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
[all …]
H A Dio.c77 return __raw_readb(OMAP1_IO_ADDRESS(pa)); in omap_readb()
83 return __raw_readw(OMAP1_IO_ADDRESS(pa)); in omap_readw()
89 return __raw_readl(OMAP1_IO_ADDRESS(pa)); in omap_readl()
95 __raw_writeb(v, OMAP1_IO_ADDRESS(pa)); in omap_writeb()
101 __raw_writew(v, OMAP1_IO_ADDRESS(pa)); in omap_writew()
107 __raw_writel(v, OMAP1_IO_ADDRESS(pa)); in omap_writel()
H A Dclock.c541 if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL)) in omap1_clk_enable_generic()
543 else if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_IDLECT2)) in omap1_clk_enable_generic()
545 else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0)) in omap1_clk_enable_generic()
547 else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1)) in omap1_clk_enable_generic()
549 else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) in omap1_clk_enable_generic()
562 if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_CKCTL)) in omap1_clk_enable_generic()
564 else if (clk->enable_reg == OMAP1_IO_ADDRESS(ARM_IDLECT2)) in omap1_clk_enable_generic()
566 else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0)) in omap1_clk_enable_generic()
568 else if (clk->enable_reg == OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1)) in omap1_clk_enable_generic()
570 else if (clk->enable_reg == OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL)) in omap1_clk_enable_generic()
[all …]
H A Dsram.S25 mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
26 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
27 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
29 mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
30 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
31 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
H A Dpm.h44 #define CLKGEN_REG_ASM_BASE OMAP1_IO_ADDRESS(0xfffece00)
48 #define TCMIF_ASM_BASE OMAP1_IO_ADDRESS(0xfffecc00)
H A Dmtd-xip.h27 ((volatile xip_omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
H A Dreset.c51 rs = __raw_readw(OMAP1_IO_ADDRESS(ARM_SYSST)); in omap1_get_reset_sources()
H A Dhardware.h65 #define OMAP1_IO_ADDRESS(pa) IOMEM((pa) - OMAP1_IO_OFFSET) macro
H A Dtime.c71 ((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \