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Searched refs:ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h15992 #define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK macro
H A Ddcn_3_0_1_sh_mask.h26337 #define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK macro
H A Ddcn_3_2_1_sh_mask.h27662 #define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK macro
H A Ddcn_2_1_0_sh_mask.h32473 #define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK macro
H A Ddcn_3_5_1_sh_mask.h23776 #define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK macro
H A Ddcn_3_5_0_sh_mask.h23797 #define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK macro
H A Ddcn_3_1_2_sh_mask.h32630 #define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK macro
H A Ddcn_3_1_5_sh_mask.h30496 #define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK macro
H A Ddcn_3_1_6_sh_mask.h33394 #define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK macro
H A Ddcn_3_1_4_sh_mask.h34500 #define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK macro
H A Ddcn_3_0_2_sh_mask.h30551 #define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK macro
H A Ddcn_2_0_0_sh_mask.h35798 #define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK macro
H A Ddcn_3_0_0_sh_mask.h34921 #define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK macro
H A Ddcn_3_2_0_sh_mask.h27686 #define ODM_MEM_PWR_CTRL__ODM_MEM2_PWR_DIS_MASK macro