Searched refs:NumDispClkLevelsEnabled (Results 1 – 14 of 14) sorted by relevance
117 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member144 uint8_t NumDispClkLevelsEnabled; // Applies to both Dispclk and Dppclk member
1081 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn35_clk_mgr_helper_populate_bw_params()1082 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn35_clk_mgr_helper_populate_bw_params()1084 clock_table->NumDispClkLevelsEnabled); in dcn35_clk_mgr_helper_populate_bw_params()1086 clock_table->NumDispClkLevelsEnabled); in dcn35_clk_mgr_helper_populate_bw_params()1162 bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()1163 bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = clock_table->NumDispClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()1406 smu_dpm_clks_b->dpm_clks->NumDispClkLevelsEnabled = in translate_to_DpmClocks_t_dcn35()1407 smu_dpm_clks_a->dpm_clks->NumDispClkLevelsEnabled; in translate_to_DpmClocks_t_dcn35()1525 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn35_clk_mgr_construct()1537 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn35_clk_mgr_construct()
134 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member162 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
120 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
132 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
133 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
145 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk member
594 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn31_clk_mgr_helper_populate_bw_params()595 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn31_clk_mgr_helper_populate_bw_params()596 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn31_clk_mgr_helper_populate_bw_params()597 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn31_clk_mgr_helper_populate_bw_params()766 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn31_clk_mgr_construct()777 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn31_clk_mgr_construct()
141 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
653 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn314_clk_mgr_helper_populate_bw_params()654 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn314_clk_mgr_helper_populate_bw_params()655 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()656 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()882 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn314_clk_mgr_construct()893 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn314_clk_mgr_construct()
60 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
79 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
87 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
116 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk member