Searched refs:NumDispClkLevelsEnabled (Results 1 – 11 of 11) sorted by relevance
117 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member144 uint8_t NumDispClkLevelsEnabled; // Applies to both Dispclk and Dppclk member
1059 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn35_clk_mgr_helper_populate_bw_params()1060 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn35_clk_mgr_helper_populate_bw_params()1062 clock_table->NumDispClkLevelsEnabled); in dcn35_clk_mgr_helper_populate_bw_params()1064 clock_table->NumDispClkLevelsEnabled); in dcn35_clk_mgr_helper_populate_bw_params()1139 bw_params->clk_table.num_entries_per_clk.num_dispclk_levels = clock_table->NumDispClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()1140 bw_params->clk_table.num_entries_per_clk.num_dppclk_levels = clock_table->NumDispClkLevelsEnabled; in dcn35_clk_mgr_helper_populate_bw_params()1383 smu_dpm_clks_b->dpm_clks->NumDispClkLevelsEnabled = in translate_to_DpmClocks_t_dcn35()1384 smu_dpm_clks_a->dpm_clks->NumDispClkLevelsEnabled; in translate_to_DpmClocks_t_dcn35()1501 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn35_clk_mgr_construct()1513 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn35_clk_mgr_construct()
60 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
120 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
132 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
133 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
145 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk member
79 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
87 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
116 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk member
141 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member