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Searched refs:MinClock (Results 1 – 25 of 30) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_smu11_driver_if.h25 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) member
H A Ddcn30_clk_mgr.c342 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu10_driver_if.h51 uint16_t MinClock; /* This is either DCFCLK or SOCCLK (in MHz) */ member
H A Dsmu9_driver_if.h330 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz) member
H A Dsmu11_driver_if.h681 uint16_t MinClock; member
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_5.h52 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu13_driver_if_yellow_carp.h50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu12_driver_if.h51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu13_driver_if_v13_0_4.h51 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu11_driver_if_vangogh.h50 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.h42 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.h41 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h56 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_smu.h49 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Ddcn35_clk_mgr.c878 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn35_build_watermark_ranges()
894 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0; in dcn35_build_watermark_ranges()
907 table->WatermarkRow[WM_DCFCLK][0].MinClock = 0; in dcn35_build_watermark_ranges()
913 table->WatermarkRow[WM_SOCCLK][0].MinClock = 0; in dcn35_build_watermark_ranges()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_smu.h52 uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu_helper.c726 table->WatermarkRow[1][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
747 table->WatermarkRow[0][i].MinClock = in smu_set_watermarks_for_clocks_ranges()
H A Dsmu_helper.h36 uint16_t MinClock; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c428 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table()
442 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_5_set_watermarks_table()
H A Dsmu_v13_0_4_ppt.c684 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table()
698 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v13_0_4_set_watermarks_table()
H A Dyellow_carp_ppt.c519 table->WatermarkRow[WM_DCFCLK][i].MinClock = in yellow_carp_set_watermarks_table()
533 table->WatermarkRow[WM_SOCCLK][i].MinClock = in yellow_carp_set_watermarks_table()
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/
H A Dsmu9_driver_if.h574 uint16_t MinClock; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0_0_ppt.c588 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v15_0_0_set_watermarks_table()
602 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v15_0_0_set_watermarks_table()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Drenoir_ppt.c1068 table->WatermarkRow[WM_DCFCLK][i].MinClock = in renoir_set_watermarks_table()
1084 table->WatermarkRow[WM_SOCCLK][i].MinClock = in renoir_set_watermarks_table()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_0_ppt.c501 table->WatermarkRow[WM_DCFCLK][i].MinClock = in smu_v14_0_0_set_watermarks_table()
515 table->WatermarkRow[WM_SOCCLK][i].MinClock = in smu_v14_0_0_set_watermarks_table()

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