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Searched refs:MaxClock (Results 1 – 25 of 35) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c358 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn316_build_watermark_ranges()
374 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn316_build_watermark_ranges()
377 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn316_build_watermark_ranges()
388 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn316_build_watermark_ranges()
393 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in dcn316_build_watermark_ranges()
H A Ddcn316_smu.h42 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c401 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
417 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
420 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
431 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
436 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in vg_build_watermark_ranges()
H A Ddcn301_smu.h57 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c436 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
452 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
455 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
466 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
471 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
H A Ddcn31_smu.h53 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c396 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn315_build_watermark_ranges()
412 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn315_build_watermark_ranges()
415 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn315_build_watermark_ranges()
426 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn315_build_watermark_ranges()
431 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in dcn315_build_watermark_ranges()
H A Ddcn315_smu.h43 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_smu11_driver_if.h26 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu10_driver_if.h52 uint16_t MaxClock; /* This is either DCFCLK or SOCCLK (in MHz) */ member
H A Dsmu9_driver_if.h331 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c501 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges()
517 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges()
520 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges()
531 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges()
536 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges()
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_5.h53 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu13_driver_if_yellow_carp.h51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu12_driver_if.h52 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu13_driver_if_v13_0_4.h52 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu11_driver_if_vangogh.h51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu14_driver_if_v14_0_0.h47 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_smu.h50 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Ddcn35_clk_mgr.c657 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn35_build_watermark_ranges()
673 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn35_build_watermark_ranges()
676 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn35_build_watermark_ranges()
687 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn35_notify_wm_ranges()
692 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in dcn35_notify_wm_ranges()
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dsmu_helper.c732 table->WatermarkRow[1][i].MaxClock = in smu_set_watermarks_for_clocks_ranges()
753 table->WatermarkRow[0][i].MaxClock = in smu_set_watermarks_for_clocks_ranges()
H A Dsmu_helper.h37 uint16_t MaxClock; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c424 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v13_0_5_set_watermarks_table()
438 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in smu_v13_0_5_set_watermarks_table()
H A Dsmu_v13_0_4_ppt.c680 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v13_0_4_set_watermarks_table()
694 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in smu_v13_0_4_set_watermarks_table()
H A Dyellow_carp_ppt.c515 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in yellow_carp_set_watermarks_table()
529 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in yellow_carp_set_watermarks_table()

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