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Searched refs:MaxClock (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_smu11_driver_if.h26 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu10_driver_if.h52 uint16_t MaxClock; /* This is either DCFCLK or SOCCLK (in MHz) */ member
H A Dsmu9_driver_if.h331 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) member
H A Dsmu11_driver_if.h682 uint16_t MaxClock; member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c443 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
459 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
462 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
473 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
478 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in dcn31_build_watermark_ranges()
H A Ddcn31_smu.h53 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_5.h53 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu13_driver_if_yellow_carp.h51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu12_driver_if.h52 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu13_driver_if_v13_0_4.h52 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu11_driver_if_vangogh.h51 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu15_driver_if_v15_0_0.h47 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Dsmu11_driver_if_navi10.h1024 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) member
H A Dsmu11_driver_if_sienna_cichlid.h1622 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.h43 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_smu.h42 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.h57 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c514 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges()
530 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges()
533 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges()
544 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges()
549 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in dcn314_build_watermark_ranges()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_smu.h50 uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz) member
H A Ddcn35_clk_mgr.c900 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn35_build_watermark_ranges()
916 table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF; in dcn35_build_watermark_ranges()
919 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn35_build_watermark_ranges()
930 table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF; in dcn35_build_watermark_ranges()
935 table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF; in dcn35_build_watermark_ranges()
/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_5_ppt.c430 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v13_0_5_set_watermarks_table()
444 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in smu_v13_0_5_set_watermarks_table()
H A Dsmu_v13_0_4_ppt.c686 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v13_0_4_set_watermarks_table()
700 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in smu_v13_0_4_set_watermarks_table()
H A Dyellow_carp_ppt.c521 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in yellow_carp_set_watermarks_table()
535 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in yellow_carp_set_watermarks_table()
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/
H A Dsmu9_driver_if.h575 uint16_t MaxClock; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu15/
H A Dsmu_v15_0_0_ppt.c670 table->WatermarkRow[WM_DCFCLK][i].MaxClock = in smu_v15_0_0_set_watermarks_table()
684 table->WatermarkRow[WM_SOCCLK][i].MaxClock = in smu_v15_0_0_set_watermarks_table()