Home
last modified time | relevance | path

Searched refs:MaxActiveDRAMClockChangeLatencySupported (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/
H A Ddml2_core_shared_types.h527 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES];
979 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES];
1762 double *MaxActiveDRAMClockChangeLatencySupported;
526 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES]; global() member
978 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES]; global() member
1759 double *MaxActiveDRAMClockChangeLatencySupported; global() member
H A Ddml2_core_dcn4.c703 if (core->clean_me_up.mode_lib.mp.MaxActiveDRAMClockChangeLatencySupported[plane_index] >= core->clean_me_up.mode_lib.soc.power_management_parameters.dram_clk_change_blackout_us) in core_dcn4_mode_programming()
H A Ddml2_core_dcn4_calcs.c6910 p->MaxActiveDRAMClockChangeLatencySupported[k] = dml_is_phantom_pipe(&p->display_cfg->plane_descriptors[k]) ? 0 : (s->ActiveDRAMClockChangeLatencyMargin[k] + p->mmSOCParameters.DRAMClockChangeLatency); in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
7977 CalculateWatermarks_params->MaxActiveDRAMClockChangeLatencySupported = &s->dummy_single_array[0]; // double *MaxActiveDRAMClockChangeLatencySupported[] in dml_core_mode_support()
11793 CalculateWatermarks_params->MaxActiveDRAMClockChangeLatencySupported = mode_lib->mp.MaxActiveDRAMClockChangeLatencySupported; in dml_core_mode_programming()
13391 out->informative.misc.MaxActiveDRAMClockChangeLatencySupported[k] = mode_lib->mp.MaxActiveDRAMClockChangeLatencySupported[k]; in dml2_core_calcs_get_informative()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_util_32.h828 double MaxActiveDRAMClockChangeLatencySupported[],
H A Ddisplay_mode_vba_32.c1219 v->MaxActiveDRAMClockChangeLatencySupported, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3624 &v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.dummy_single2[0], // double *MaxActiveDRAMClockChangeLatencySupported in dml32_ModeSupportAndSystemConfigurationFull()
/linux/drivers/gpu/drm/amd/display/dc/dml2_0/
H A Ddisplay_mode_core_structs.h1254 dml_float_t MaxActiveDRAMClockChangeLatencySupported[__DML_NUM_PLANES__]; member
1382 dml_float_t *MaxActiveDRAMClockChangeLatencySupported; member
H A Ddisplay_mode_core.c2999 p->MaxActiveDRAMClockChangeLatencySupported[k] = (p->UseMALLForPStateChange[k] == dml_use_mall_pstate_change_phantom_pipe) ? 0 : (s->ActiveDRAMClockChangeLatencyMargin[k] + p->mmSOCParameters.DRAMClockChangeLatency); in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6810 CalculateWatermarks_params->MaxActiveDRAMClockChangeLatencySupported = &s->dummy_single_array[0]; // dml_float_t *MaxActiveDRAMClockChangeLatencySupported[] in dml_core_mode_support()
9583 CalculateWatermarks_params->MaxActiveDRAMClockChangeLatencySupported = locals->MaxActiveDRAMClockChangeLatencySupported; // dml_float_t *MaxActiveDRAMClockChangeLatencySupported[] in dml_core_mode_programming()
10448 dml_get_per_surface_var_func(max_active_dram_clock_change_latency_supported, dml_uint_t, mode_lib->mp.MaxActiveDRAMClockChangeLatencySupported);
/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.h1224 double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX]; member