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Searched refs:M_MASK (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/bridge/imx/
H A Dimx93-mipi-dsi.c41 #define M_MASK GENMASK(9, 0) macro
42 #define M(x) FIELD_PREP(M_MASK, ((x) - 2))
/linux/drivers/atm/
H A Diphase.c315 #define M_MASK 0x1ff in cellrate_to_float() macro
327 flot = NZ | (i << M_BITS) | (cr & M_MASK); in cellrate_to_float()
329 flot = NZ | (i << M_BITS) | ((cr << (M_BITS - i)) & M_MASK); in cellrate_to_float()
331 flot = NZ | (i << M_BITS) | ((cr >> (i - M_BITS)) & M_MASK); in cellrate_to_float()
346 mantissa = rate & M_MASK;
/linux/arch/powerpc/xmon/
H A Dppc-opc.c2461 #define M_MASK M (0x3f, 1) macro
2471 #define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)
2474 #define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)
4587 {"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4588 {"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4590 {"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4591 {"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4595 {"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4596 {"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
4599 {"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}},
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/linux/drivers/iommu/
H A Dmsm_iommu_hw-8xxx.h1123 #define M (M_MASK << M_SHIFT)
1585 #define M_MASK 0x01 macro