Searched refs:MVPP22_XLG_CTRL0_REG (Results 1 – 2 of 2) sorted by relevance
1806 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_enable()1809 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_enable()1824 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()1826 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_disable()2174 val = readl(port->base + MVPP22_XLG_CTRL0_REG) & in mvpp2_mac_reset_assert()2176 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_mac_reset_assert()6004 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_init()6007 writel(val, port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_port_init()6254 val = readl(port->base + MVPP22_XLG_CTRL0_REG); in mvpp2_xlg_pcs_get_state()6413 mvpp2_modify(port->base + MVPP22_XLG_CTRL0_REG, in mvpp2_xlg_config()[all …]
493 #define MVPP22_XLG_CTRL0_REG 0x100 macro