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Searched refs:MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h24843 #define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h40926 #define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h16115 #define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT … macro
H A Ddcn_3_5_1_sh_mask.h43045 #define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT … macro
H A Ddcn_3_5_0_sh_mask.h43066 #define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h23739 #define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h21754 #define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h24495 #define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h56611 #define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h48063 #define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h55314 #define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT … macro
H A Ddcn_4_1_0_sh_mask.h18206 #define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h16139 #define MPCC_OGAM1_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE__SHIFT … macro