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Searched refs:MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_sh_mask.h24311 #define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK … macro
H A Ddcn_3_0_1_sh_mask.h40394 #define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK … macro
H A Ddcn_3_2_1_sh_mask.h15583 #define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK … macro
H A Ddcn_3_5_1_sh_mask.h42606 #define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK … macro
H A Ddcn_3_5_0_sh_mask.h42627 #define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK … macro
H A Ddcn_3_1_2_sh_mask.h23207 #define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK … macro
H A Ddcn_3_1_5_sh_mask.h21222 #define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK … macro
H A Ddcn_3_1_6_sh_mask.h23963 #define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK … macro
H A Ddcn_3_1_4_sh_mask.h56079 #define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK … macro
H A Ddcn_3_0_2_sh_mask.h47531 #define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK … macro
H A Ddcn_3_0_0_sh_mask.h54782 #define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK … macro
H A Ddcn_3_2_0_sh_mask.h15607 #define MPCC_OGAM0_MPCC_OGAM_CONTROL__MPCC_OGAM_MODE_MASK … macro