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Searched refs:MPCC_MCM_3DLUT_RAM_SEL (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn401/
H A Ddcn401_mpc.c289 …REG_UPDATE(MPCC_MCM_3DLUT_READ_WRITE_CONTROL[mpcc_id], MPCC_MCM_3DLUT_RAM_SEL, lut_bank_a ? 0 : 1); in mpc401_program_lut_read_write_control()
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn32/
H A Ddcn32_mpc.h242 SF(MPCC_MCM0_MPCC_MCM_3DLUT_READ_WRITE_CONTROL, MPCC_MCM_3DLUT_RAM_SEL, mask_sh),\
H A Ddcn32_mpc.c806 MPCC_MCM_3DLUT_RAM_SEL, mode == LUT_RAM_A ? 0 : 1, in mpc32_select_3dlut_ram()
/linux/drivers/gpu/drm/amd/display/dc/mpc/dcn30/
H A Ddcn30_mpc.h744 type MPCC_MCM_3DLUT_RAM_SEL;\
/linux/drivers/gpu/drm/amd/include/
H A Dsoc24_enum.h3214 typedef enum MPCC_MCM_3DLUT_RAM_SEL { enum
3219 } MPCC_MCM_3DLUT_RAM_SEL; typedef
H A Dsoc21_enum.h3143 typedef enum MPCC_MCM_3DLUT_RAM_SEL { enum
3148 } MPCC_MCM_3DLUT_RAM_SEL; typedef