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Searched refs:MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h11056 #define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_1_0_sh_mask.h19079 #define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h40296 #define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h15282 #define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h20444 #define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_5_1_sh_mask.h42529 #define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_5_0_sh_mask.h42550 #define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h22770 #define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h20785 #define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h23526 #define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h55981 #define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h47350 #define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h23512 #define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h54519 #define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h15306 #define MPCC2_MPCC_STATUS__MPCC_IDLE__SHIFT … macro