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Searched refs:MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_sh_mask.h10794 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
H A Ddcn_3_0_3_sh_mask.h24146 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
H A Ddcn_1_0_sh_mask.h18804 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
H A Ddcn_3_0_1_sh_mask.h40063 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
H A Ddcn_3_2_1_sh_mask.h15034 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h20178 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
H A Ddcn_3_5_1_sh_mask.h42341 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
H A Ddcn_3_5_0_sh_mask.h42362 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
H A Ddcn_3_1_2_sh_mask.h22537 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
H A Ddcn_3_1_5_sh_mask.h20552 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
H A Ddcn_3_1_6_sh_mask.h23293 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
H A Ddcn_3_1_4_sh_mask.h55748 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
H A Ddcn_3_0_2_sh_mask.h47117 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h23246 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h54286 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro
H A Ddcn_3_2_0_sh_mask.h15058 #define MPCC0_MPCC_OPP_ID__MPCC_OPP_ID__SHIFT … macro