Searched refs:MODULO (Results 1 – 5 of 5) sorted by relevance
| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn31/ |
| H A D | dcn31_dccg.h | 51 DCCG_SRII(MODULO, DTBCLK_DTO, 0),\
52 DCCG_SRII(MODULO, DTBCLK_DTO, 1),\
53 DCCG_SRII(MODULO, DTBCLK_DTO, 2),\
54 DCCG_SRII(MODULO, DTBCLK_DTO, 3),\
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| /linux/drivers/gpu/drm/amd/display/dc/dccg/dcn314/ |
| H A D | dcn314_dccg.h | 56 DCCG_SRII(MODULO, DTBCLK_DTO, 0),\
57 DCCG_SRII(MODULO, DTBCLK_DTO, 1),\
58 DCCG_SRII(MODULO, DTBCLK_DTO, 2),\
59 DCCG_SRII(MODULO, DTBCLK_DTO, 3),\
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| /linux/drivers/scsi/be2iscsi/ |
| H A D | be.h | 40 static inline u32 MODULO(u16 val, u16 limit) in MODULO() function
48 *index = MODULO((*index + 1), limit); in index_inc()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_clock_source.c | 990 REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor); in dcn31_program_pix_clk()
994 REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000); in dcn31_program_pix_clk()
1227 /* NOTE: In case VBLANK syncronization is enabled, MODULO may in get_pixel_clk_frequency_100hz()
1230 modulo_hz = REG_READ(MODULO[inst]); in get_pixel_clk_frequency_100hz()
1238 /* NOTE: There is agreement with VBIOS here that MODULO is
1261 modulo_hz = REG_READ(MODULO[inst]);
1284 * - DPDTO MODULO = DTBCLK_P rate in dcn20_program_pix_clk()
1285 * - target pix_clk_hz = (DPDTO INTEGER * DPDTO MODULO + DPDTO PHASE) in dcn20_program_pix_clk()
1371 REG_WRITE(MODULO[inst], in dcn3_get_pix_clk_dividers()
1387 REG_WRITE(MODULO[ins in dcn3_get_pix_clk_dividers()
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| /linux/drivers/net/ethernet/emulex/benet/ |
| H A D | be_main.c | 5491 MODULO(adapter->work_counter, adapter->be_get_temp_freq) == 0) in be_worker()
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