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Searched refs:MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v4_0.c243 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CACHE_CTRL), ~0x1, 0); in vce_v4_0_sriov_start()
299 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_CTRL2), ~0x100, 0); in vce_v4_0_sriov_start()
300 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), in vce_v4_0_sriov_start()
305 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), in vce_v4_0_sriov_start()
307 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CNTL), in vce_v4_0_sriov_start()
309 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SOFT_RESET), in vce_v4_0_sriov_start()
317 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_STATUS), in vce_v4_0_sriov_start()
H A Dmmsch_v1_0.h130 #define MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(reg, mask, data) { \ macro
H A Duvd_v7_0.c823 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in uvd_v7_0_sriov_start()
867 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), in uvd_v7_0_sriov_start()
871 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), in uvd_v7_0_sriov_start()
875 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), in uvd_v7_0_sriov_start()
908 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN), in uvd_v7_0_sriov_start()
913 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), in uvd_v7_0_sriov_start()
932 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), in uvd_v7_0_sriov_start()
H A Dvcn_v2_5.c1286 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT( in vcn_v2_5_sriov_start()