Searched refs:MM81X_REG_INT1_CLR (Results 1 – 2 of 2) sorted by relevance
192 u32 irq_clr_addr = irq < 32 ? MM81X_REG_INT1_CLR(mors) : in mm81x_hw_irq_enable()219 mm81x_reg32_write(mors, MM81X_REG_INT1_CLR(mors), status1); in mm81x_hw_irq_handle()228 mm81x_reg32_write(mors, MM81X_REG_INT1_CLR(mors), 0xFFFFFFFF); in mm81x_hw_irq_clear()
35 #define MM81X_REG_INT1_CLR(mors) (MM81X_REG_INT_BASE(mors) + 0x08) macro