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Searched refs:MLX5_ST_SZ_DW (Results 1 – 25 of 71) sorted by relevance

123

/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Dport.c89 u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0}; in mlx5_query_pcam_reg()
101 u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0}; in mlx5_query_mcam_reg()
113 u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {}; in mlx5_query_qcam_reg()
150 u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0}; in mlx5_query_port_ptys()
162 u32 in[MLX5_ST_SZ_DW(mlcr_reg)] = {0}; in mlx5_set_port_beacon()
163 u32 out[MLX5_ST_SZ_DW(mlcr_reg)]; in mlx5_set_port_beacon()
174 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_ib_port_oper()
203 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0}; in mlx5_set_port_admin_status()
204 u32 out[MLX5_ST_SZ_DW(paos_reg)]; in mlx5_set_port_admin_status()
216 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0}; in mlx5_query_port_admin_status()
[all …]
H A Dmr.c41 u32 lout[MLX5_ST_SZ_DW(create_mkey_out)] = {}; in mlx5_core_create_mkey()
62 u32 in[MLX5_ST_SZ_DW(destroy_mkey_in)] = {}; in mlx5_core_destroy_mkey()
73 u32 in[MLX5_ST_SZ_DW(query_mkey_in)] = {}; in mlx5_core_query_mkey()
95 u32 out[MLX5_ST_SZ_DW(create_psv_out)] = {}; in mlx5_core_create_psv()
96 u32 in[MLX5_ST_SZ_DW(create_psv_in)] = {}; in mlx5_core_create_psv()
119 u32 in[MLX5_ST_SZ_DW(destroy_psv_in)] = {}; in mlx5_core_destroy_psv()
129 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {}; in mlx5_core_get_terminate_scatter_list_mkey()
130 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {}; in mlx5_core_get_terminate_scatter_list_mkey()
H A Dtransobj.c39 u32 out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {}; in mlx5_core_alloc_transport_domain()
40 u32 in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {}; in mlx5_core_alloc_transport_domain()
57 u32 in[MLX5_ST_SZ_DW(dealloc_transport_domain_in)] = {}; in mlx5_core_dealloc_transport_domain()
68 u32 out[MLX5_ST_SZ_DW(create_rq_out)] = {}; in mlx5_core_create_rq()
91 u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {}; in mlx5_core_destroy_rq()
101 u32 in[MLX5_ST_SZ_DW(query_rq_in)] = {}; in mlx5_core_query_rq()
112 u32 out[MLX5_ST_SZ_DW(create_sq_out)] = {}; in mlx5_core_create_sq()
133 u32 in[MLX5_ST_SZ_DW(destroy_sq_in)] = {}; in mlx5_core_destroy_sq()
142 u32 in[MLX5_ST_SZ_DW(query_sq_in)] = {}; in mlx5_core_query_sq()
177 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; in mlx5_core_create_tir()
[all …]
H A Dhwmon.c45 u32 mtmp_in[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_query_mtmp()
56 u32 mtmp_out[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_reset_max_temp()
57 u32 mtmp_in[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_reset_max_temp()
69 u32 mtmp_out[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_enable_max_temp()
70 u32 mtmp_in[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_enable_max_temp()
87 u32 mtmp_out[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_read()
168 u32 mtmp_out[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_init_channels_names()
249 u32 mtmp_out[MLX5_ST_SZ_DW(mtmp_reg)]; in mlx5_hwmon_is_module_mon_cap()
269 u32 mtcap_out[MLX5_ST_SZ_DW(mtcap_reg)] = {}; in mlx5_hwmon_get_sensors_count()
270 u32 mtcap_in[MLX5_ST_SZ_DW(mtcap_reg)] = {}; in mlx5_hwmon_get_sensors_count()
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H A Dfw.c74 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {}; in mlx5_query_board_id()
101 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {}; in mlx5_core_query_vendor_id()
314 u32 in[MLX5_ST_SZ_DW(init_hca_in)] = {}; in mlx5_cmd_init_hca()
334 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {}; in mlx5_cmd_teardown_hca()
342 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; in mlx5_cmd_force_teardown_hca()
343 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; in mlx5_cmd_force_teardown_hca()
371 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {}; in mlx5_cmd_fast_teardown_hca()
372 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {}; in mlx5_cmd_fast_teardown_hca()
433 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; in mlx5_reg_mcc_set()
434 u32 in[MLX5_ST_SZ_DW(mcc_reg)]; in mlx5_reg_mcc_set()
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H A Dpd.c39 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; in mlx5_core_alloc_pd()
40 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; in mlx5_core_alloc_pd()
53 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {}; in mlx5_core_dealloc_pd()
H A Dcq.c113 u32 din[MLX5_ST_SZ_DW(destroy_cq_in)] = {}; in mlx5_create_cq()
192 u32 in[MLX5_ST_SZ_DW(destroy_cq_in)] = {}; in mlx5_core_destroy_cq()
218 u32 in[MLX5_ST_SZ_DW(query_cq_in)] = {}; in mlx5_core_query_cq()
229 u32 out[MLX5_ST_SZ_DW(modify_cq_out)] = {}; in mlx5_core_modify_cq()
242 u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {}; in mlx5_core_modify_cq_moderation()
H A Dqos.c29 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; in mlx5_qos_create_leaf_node()
49 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; in mlx5_qos_create_inner_node()
81 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; in mlx5_qos_update_node()
H A Dvport.c47 u32 out[MLX5_ST_SZ_DW(query_vport_state_out)] = {}; in mlx5_query_vport_state()
48 u32 in[MLX5_ST_SZ_DW(query_vport_state_in)] = {}; in mlx5_query_vport_state()
69 u32 out[MLX5_ST_SZ_DW(query_vport_state_out)] = {}; in mlx5_query_vport_admin_state()
70 u32 in[MLX5_ST_SZ_DW(query_vport_state_in)] = {}; in mlx5_query_vport_admin_state()
90 u32 in[MLX5_ST_SZ_DW(modify_vport_state_in)] = {}; in mlx5_modify_vport_admin_state()
133 u32 in[MLX5_ST_SZ_DW(modify_vport_state_in)] = {}; in mlx5_modify_vport_max_tx_speed()
161 u32 out[MLX5_ST_SZ_DW(query_vport_state_out)] = {}; in mlx5_query_vport_max_tx_speed()
162 u32 in[MLX5_ST_SZ_DW(query_vport_state_in)] = {}; in mlx5_query_vport_max_tx_speed()
185 u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {}; in mlx5_query_nic_vport_context()
198 u32 out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {}; in mlx5_query_nic_vport_min_inline()
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H A Dmcg.c40 u32 in[MLX5_ST_SZ_DW(attach_to_mcg_in)] = {}; in mlx5_core_attach_mcg()
53 u32 in[MLX5_ST_SZ_DW(detach_from_mcg_in)] = {}; in mlx5_core_detach_mcg()
H A Den_stats.c616 u32 out[MLX5_ST_SZ_DW(query_q_counter_out)] = {}; in MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS()
617 u32 in[MLX5_ST_SZ_DW(query_q_counter_in)] = {}; in MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS()
719 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {}; in MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS()
822 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)] = {}; in MLX5E_DECLARE_STATS_GRP_OP_UPDATE_STATS()
886 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {0};
907 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {}; in mlx5e_stats_get_ieee()
922 u32 in[MLX5_ST_SZ_DW(ppcnt_reg)] = {}; in mlx5e_stats_get_per_prio()
939 u32 ppcnt_ieee_802_3[MLX5_ST_SZ_DW(ppcnt_reg)]; in mlx5e_stats_pause_get()
971 u32 ppcnt_ieee_802_3[MLX5_ST_SZ_DW(ppcnt_reg)]; in mlx5e_stats_eth_phy_get()
986 u32 ppcnt_ieee_802_3[MLX5_ST_SZ_DW(ppcnt_reg)]; in mlx5e_stats_eth_mac_get()
[all …]
/linux/drivers/net/ethernet/mellanox/mlx5/core/sf/
H A Dcmd.c9 u32 out[MLX5_ST_SZ_DW(alloc_sf_out)] = {}; in mlx5_cmd_alloc_sf()
10 u32 in[MLX5_ST_SZ_DW(alloc_sf_in)] = {}; in mlx5_cmd_alloc_sf()
20 u32 out[MLX5_ST_SZ_DW(dealloc_sf_out)] = {}; in mlx5_cmd_dealloc_sf()
21 u32 in[MLX5_ST_SZ_DW(dealloc_sf_in)] = {}; in mlx5_cmd_dealloc_sf()
31 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {}; in mlx5_cmd_sf_enable_hca()
32 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; in mlx5_cmd_sf_enable_hca()
42 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {}; in mlx5_cmd_sf_disable_hca()
43 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; in mlx5_cmd_sf_disable_hca()
H A Dvhca_event.c29 u32 in[MLX5_ST_SZ_DW(query_vhca_state_in)] = {}; in mlx5_cmd_query_vhca_state()
41 u32 out[MLX5_ST_SZ_DW(modify_vhca_state_out)] = {}; in mlx5_cmd_modify_vhca_state()
52 u32 out[MLX5_ST_SZ_DW(modify_vhca_state_out)] = {}; in mlx5_modify_vhca_sw_id()
53 u32 in[MLX5_ST_SZ_DW(modify_vhca_state_in)] = {}; in mlx5_modify_vhca_sw_id()
66 u32 in[MLX5_ST_SZ_DW(modify_vhca_state_in)] = {}; in mlx5_vhca_event_arm()
77 u32 out[MLX5_ST_SZ_DW(query_vhca_state_out)] = {}; in mlx5_vhca_event_notify()
/linux/drivers/net/ethernet/mellanox/mlx5/core/fpga/
H A Dcmd.c40 #define MLX5_FPGA_ACCESS_REG_SZ (MLX5_ST_SZ_DW(fpga_access_reg) + \
75 u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0}; in mlx5_fpga_caps()
84 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_ctrl_op()
85 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_ctrl_op()
127 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_query()
128 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_query()
145 u32 out[MLX5_ST_SZ_DW(fpga_create_qp_out)] = {}; in mlx5_fpga_create_qp()
146 u32 in[MLX5_ST_SZ_DW(fpga_create_qp_in)] = {}; in mlx5_fpga_create_qp()
167 u32 in[MLX5_ST_SZ_DW(fpga_modify_qp_in)] = {}; in mlx5_fpga_modify_qp()
181 u32 out[MLX5_ST_SZ_DW(fpga_query_qp_out)] = {}; in mlx5_fpga_query_qp()
[all …]
/linux/drivers/infiniband/hw/mlx5/
H A Dcmd.c10 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {}; in mlx5r_cmd_query_special_mkeys()
11 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {}; in mlx5r_cmd_query_special_mkeys()
48 u32 in[MLX5_ST_SZ_DW(query_cong_params_in)] = {}; in mlx5_cmd_query_cong_params()
59 u32 in[MLX5_ST_SZ_DW(destroy_tir_in)] = {}; in mlx5_cmd_destroy_tir()
69 u32 in[MLX5_ST_SZ_DW(destroy_tis_in)] = {}; in mlx5_cmd_destroy_tis()
79 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {}; in mlx5_cmd_destroy_rqt()
90 u32 in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {}; in mlx5_cmd_alloc_transport_domain()
91 u32 out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {}; in mlx5_cmd_alloc_transport_domain()
109 u32 in[MLX5_ST_SZ_DW(dealloc_transport_domain_in)] = {}; in mlx5_cmd_dealloc_transport_domain()
120 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {}; in mlx5_cmd_dealloc_pd()
[all …]
/linux/drivers/vdpa/mlx5/core/
H A Dresources.c18 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; in alloc_pd()
19 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; in alloc_pd()
34 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {}; in dealloc_pd()
45 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {}; in get_null_mkey()
46 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {}; in get_null_mkey()
59 u32 out[MLX5_ST_SZ_DW(create_uctx_out)] = {}; in create_uctx()
89 u32 out[MLX5_ST_SZ_DW(destroy_uctx_out)] = {}; in destroy_uctx()
90 u32 in[MLX5_ST_SZ_DW(destroy_uctx_in)] = {}; in destroy_uctx()
103 u32 out[MLX5_ST_SZ_DW(create_tis_out)] = {}; in mlx5_vdpa_create_tis()
117 u32 in[MLX5_ST_SZ_DW(destroy_tis_in)] = {}; in mlx5_vdpa_destroy_tis()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/
H A Dcmd.c37 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {}; in hws_cmd_general_obj_destroy()
38 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; in hws_cmd_general_obj_destroy()
51 u32 out[MLX5_ST_SZ_DW(create_flow_table_out)] = {0}; in mlx5hws_cmd_flow_table_create()
52 u32 in[MLX5_ST_SZ_DW(create_flow_table_in)] = {0}; in mlx5hws_cmd_flow_table_create()
79 u32 in[MLX5_ST_SZ_DW(modify_flow_table_in)] = {0}; in mlx5hws_cmd_flow_table_modify()
102 u32 out[MLX5_ST_SZ_DW(query_flow_table_out)] = {0}; in mlx5hws_cmd_flow_table_query()
103 u32 in[MLX5_ST_SZ_DW(query_flow_table_in)] = {0}; in mlx5hws_cmd_flow_table_query()
125 u32 in[MLX5_ST_SZ_DW(destroy_flow_table_in)] = {0}; in mlx5hws_cmd_flow_table_destroy()
138 u32 out[MLX5_ST_SZ_DW(create_flow_group_out)] = {0}; in hws_cmd_flow_group_create()
165 u32 in[MLX5_ST_SZ_DW(destroy_flow_group_in)] = {}; in hws_cmd_flow_group_destroy()
[all …]
/linux/drivers/net/ethernet/mellanox/mlx5/core/en/
H A Dport.c38 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_query_eth_autoneg()
55 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_set_eth_ptys()
56 u32 in[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_set_eth_ptys()
147 u32 in[MLX5_ST_SZ_DW(sbpr_reg)] = {}; in mlx5e_port_query_sbpr()
159 u32 out[MLX5_ST_SZ_DW(sbpr_reg)] = {}; in mlx5e_port_set_sbpr()
160 u32 in[MLX5_ST_SZ_DW(sbpr_reg)] = {}; in mlx5e_port_set_sbpr()
176 u32 in[MLX5_ST_SZ_DW(sbcm_reg)] = {}; in mlx5e_port_query_sbcm()
189 u32 out[MLX5_ST_SZ_DW(sbcm_reg)] = {}; in mlx5e_port_set_sbcm()
190 u32 in[MLX5_ST_SZ_DW(sbcm_reg)] = {}; in mlx5e_port_set_sbcm()
468 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {}; in mlx5e_fec_in_caps()
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H A Dtir.c12 MLX5_ST_SZ_DW(create_tir_in) > MLX5_ST_SZ_DW(modify_tir_in) ? \
13 MLX5_ST_SZ_DW(create_tir_in) : MLX5_ST_SZ_DW(modify_tir_in) \
H A Dmonitor_stats.c50 u32 in[MLX5_ST_SZ_DW(arm_monitor_counter_in)] = {}; in mlx5e_monitor_counter_arm()
118 u32 in[MLX5_ST_SZ_DW(set_monitor_counter_in)] = {}; in mlx5e_set_monitor_counter()
157 u32 in[MLX5_ST_SZ_DW(set_monitor_counter_in)] = {}; in mlx5e_monitor_counter_cleanup()
/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dgeneve.c22 u32 in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {}; in mlx5_geneve_tlv_option_create()
23 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; in mlx5_geneve_tlv_option_create()
53 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; in mlx5_geneve_tlv_option_destroy()
54 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {}; in mlx5_geneve_tlv_option_destroy()
H A Dnv_param.c258 u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {}; in mlx5_nv_param_devlink_cqe_compress_get()
300 u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {}; in mlx5_nv_param_devlink_cqe_compress_set()
338 u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {}; in mlx5_swp_l4_csum_mode_get()
387 u32 cap[MLX5_ST_SZ_DW(mnvda_reg)] = {}; in mlx5_devlink_swp_l4_csum_mode_validate()
427 u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {}; in mlx5_swp_l4_csum_mode_set()
537 u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {}; in mlx5_devlink_enable_sriov_get()
581 u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {}; in mlx5_devlink_enable_sriov_set()
649 u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)] = {}; in mlx5_devlink_total_vfs_get()
690 u32 mnvda[MLX5_ST_SZ_DW(mnvda_reg)]; in mlx5_devlink_total_vfs_set()
740 u32 cap[MLX5_ST_SZ_DW(mnvda_reg)]; in mlx5_devlink_total_vfs_validate()
[all …]
H A Dcrypto.c138 u32 in[MLX5_ST_SZ_DW(sync_crypto_in)] = {}; in mlx5_crypto_cmd_sync_crypto()
161 u32 in[MLX5_ST_SZ_DW(create_encryption_key_in)] = {}; in mlx5_crypto_create_dek_bulk()
162 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; in mlx5_crypto_create_dek_bulk()
192 u32 in[MLX5_ST_SZ_DW(modify_encryption_key_in)] = {}; in mlx5_crypto_modify_dek_key()
193 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; in mlx5_crypto_modify_dek_key()
227 u32 in[MLX5_ST_SZ_DW(create_encryption_key_in)] = {}; in mlx5_crypto_create_dek_key()
228 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; in mlx5_crypto_create_dek_key()
263 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {}; in mlx5_crypto_destroy_dek_key()
264 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; in mlx5_crypto_destroy_dek_key()
/linux/drivers/net/ethernet/mellanox/mlx5/core/esw/
H A Dadj_vport.c10 u32 in[MLX5_ST_SZ_DW(modify_vport_state_in)] = {}; in mlx5_esw_adj_vport_modify()
50 u32 in[MLX5_ST_SZ_DW(destroy_esw_vport_in)] = {}; in mlx5_esw_destroy_esw_vport()
62 u32 out[MLX5_ST_SZ_DW(create_esw_vport_out)] = {}; in mlx5_esw_create_esw_vport()
63 u32 in[MLX5_ST_SZ_DW(create_esw_vport_in)] = {}; in mlx5_esw_create_esw_vport()
168 u32 in[MLX5_ST_SZ_DW(query_delegated_vhca_in)] = {}; in mlx5_esw_adjacent_vhcas_setup()
/linux/drivers/net/ethernet/mellanox/mlx5/core/diag/
H A Dfw_tracer.c43 u32 out[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_query_mtrc_caps()
44 u32 in[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_query_mtrc_caps()
87 u32 in[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_set_mtrc_caps_trace_owner()
98 u32 out[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_fw_tracer_ownership_acquire()
119 u32 out[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_fw_tracer_ownership_release()
271 u32 in[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_tracer_read_strings_db()
346 u32 out[MLX5_ST_SZ_DW(mtrc_ctrl)] = {0}; in mlx5_fw_tracer_arm()
347 u32 in[MLX5_ST_SZ_DW(mtrc_ctrl)] = {0}; in mlx5_fw_tracer_arm()
844 u32 out[MLX5_ST_SZ_DW(mtrc_conf)] = {0}; in mlx5_fw_tracer_set_mtrc_conf()
845 u32 in[MLX5_ST_SZ_DW(mtrc_conf)] = {0}; in mlx5_fw_tracer_set_mtrc_conf()
[all …]

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