/linux/drivers/net/ethernet/mellanox/mlx5/core/ |
H A D | port.c | 89 u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0}; in mlx5_query_pcam_reg() 101 u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0}; in mlx5_query_mcam_reg() 113 u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {}; in mlx5_query_qcam_reg() 150 u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0}; in mlx5_query_port_ptys() 162 u32 in[MLX5_ST_SZ_DW(mlcr_reg)] = {0}; in mlx5_set_port_beacon() 163 u32 out[MLX5_ST_SZ_DW(mlcr_reg)]; in mlx5_set_port_beacon() 174 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_ib_port_oper() 204 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0}; in mlx5_set_port_admin_status() 205 u32 out[MLX5_ST_SZ_DW(paos_reg)]; in mlx5_set_port_admin_status() 218 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0}; in mlx5_query_port_admin_status() [all …]
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H A D | mr.c | 41 u32 lout[MLX5_ST_SZ_DW(create_mkey_out)] = {}; in mlx5_core_create_mkey() 62 u32 in[MLX5_ST_SZ_DW(destroy_mkey_in)] = {}; in mlx5_core_destroy_mkey() 73 u32 in[MLX5_ST_SZ_DW(query_mkey_in)] = {}; in mlx5_core_query_mkey() 95 u32 out[MLX5_ST_SZ_DW(create_psv_out)] = {}; in mlx5_core_create_psv() 96 u32 in[MLX5_ST_SZ_DW(create_psv_in)] = {}; in mlx5_core_create_psv() 119 u32 in[MLX5_ST_SZ_DW(destroy_psv_in)] = {}; in mlx5_core_destroy_psv() 129 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {}; in mlx5_core_get_terminate_scatter_list_mkey() 130 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {}; in mlx5_core_get_terminate_scatter_list_mkey()
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H A D | transobj.c | 39 u32 out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {}; in mlx5_core_alloc_transport_domain() 40 u32 in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {}; in mlx5_core_alloc_transport_domain() 57 u32 in[MLX5_ST_SZ_DW(dealloc_transport_domain_in)] = {}; in mlx5_core_dealloc_transport_domain() 68 u32 out[MLX5_ST_SZ_DW(create_rq_out)] = {}; in mlx5_core_create_rq() 91 u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {}; in mlx5_core_destroy_rq() 101 u32 in[MLX5_ST_SZ_DW(query_rq_in)] = {}; in mlx5_core_query_rq() 112 u32 out[MLX5_ST_SZ_DW(create_sq_out)] = {}; in mlx5_core_create_sq() 133 u32 in[MLX5_ST_SZ_DW(destroy_sq_in)] = {}; in mlx5_core_destroy_sq() 142 u32 in[MLX5_ST_SZ_DW(query_sq_in)] = {}; in mlx5_core_query_sq() 177 u32 out[MLX5_ST_SZ_DW(create_tir_out)] = {}; in mlx5_core_create_tir() [all …]
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H A D | hwmon.c | 45 u32 mtmp_in[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_query_mtmp() 56 u32 mtmp_out[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_reset_max_temp() 57 u32 mtmp_in[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_reset_max_temp() 69 u32 mtmp_out[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_enable_max_temp() 70 u32 mtmp_in[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_enable_max_temp() 87 u32 mtmp_out[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_read() 168 u32 mtmp_out[MLX5_ST_SZ_DW(mtmp_reg)] = {}; in mlx5_hwmon_init_channels_names() 249 u32 mtmp_out[MLX5_ST_SZ_DW(mtmp_reg)]; in mlx5_hwmon_is_module_mon_cap() 269 u32 mtcap_out[MLX5_ST_SZ_DW(mtcap_reg)] = {}; in mlx5_hwmon_get_sensors_count() 270 u32 mtcap_in[MLX5_ST_SZ_DW(mtcap_reg)] = {}; in mlx5_hwmon_get_sensors_count() [all …]
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H A D | ecpf.c | 22 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {}; in mlx5_cmd_host_pf_enable_hca() 23 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; in mlx5_cmd_host_pf_enable_hca() 33 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {}; in mlx5_cmd_host_pf_disable_hca() 34 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; in mlx5_cmd_host_pf_disable_hca()
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H A D | pd.c | 39 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; in mlx5_core_alloc_pd() 40 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; in mlx5_core_alloc_pd() 53 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {}; in mlx5_core_dealloc_pd()
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H A D | qos.c | 29 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; in mlx5_qos_create_leaf_node() 49 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; in mlx5_qos_create_inner_node() 81 u32 sched_ctx[MLX5_ST_SZ_DW(scheduling_context)] = {0}; in mlx5_qos_update_node()
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H A D | vport.c | 46 u32 out[MLX5_ST_SZ_DW(query_vport_state_out)] = {}; in mlx5_query_vport_state() 47 u32 in[MLX5_ST_SZ_DW(query_vport_state_in)] = {}; in mlx5_query_vport_state() 67 u32 in[MLX5_ST_SZ_DW(modify_vport_state_in)] = {}; in mlx5_modify_vport_admin_state() 82 u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {}; in mlx5_query_nic_vport_context() 96 u32 out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {}; in mlx5_query_nic_vport_min_inline() 128 u32 in[MLX5_ST_SZ_DW(modify_nic_vport_context_in)] = {}; in mlx5_modify_nic_vport_min_inline() 149 u32 out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {}; in mlx5_query_nic_vport_mac_address() 150 u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {}; in mlx5_query_nic_vport_mac_address() 259 u32 in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0}; in mlx5_query_nic_vport_mac_list() 321 u32 out[MLX5_ST_SZ_DW(modify_nic_vport_context_out)] = {}; in mlx5_modify_nic_vport_mac_list() [all …]
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H A D | mcg.c | 40 u32 in[MLX5_ST_SZ_DW(attach_to_mcg_in)] = {}; in mlx5_core_attach_mcg() 53 u32 in[MLX5_ST_SZ_DW(detach_from_mcg_in)] = {}; in mlx5_core_detach_mcg()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/fpga/ |
H A D | cmd.c | 40 #define MLX5_FPGA_ACCESS_REG_SZ (MLX5_ST_SZ_DW(fpga_access_reg) + \ 75 u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0}; in mlx5_fpga_caps() 84 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_ctrl_op() 85 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_ctrl_op() 127 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_query() 128 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_query() 145 u32 out[MLX5_ST_SZ_DW(fpga_create_qp_out)] = {}; in mlx5_fpga_create_qp() 146 u32 in[MLX5_ST_SZ_DW(fpga_create_qp_in)] = {}; in mlx5_fpga_create_qp() 167 u32 in[MLX5_ST_SZ_DW(fpga_modify_qp_in)] = {}; in mlx5_fpga_modify_qp() 181 u32 out[MLX5_ST_SZ_DW(fpga_query_qp_out)] = {}; in mlx5_fpga_query_qp() [all …]
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/linux/drivers/net/ethernet/mellanox/mlx5/core/sf/ |
H A D | cmd.c | 9 u32 out[MLX5_ST_SZ_DW(alloc_sf_out)] = {}; in mlx5_cmd_alloc_sf() 10 u32 in[MLX5_ST_SZ_DW(alloc_sf_in)] = {}; in mlx5_cmd_alloc_sf() 20 u32 out[MLX5_ST_SZ_DW(dealloc_sf_out)] = {}; in mlx5_cmd_dealloc_sf() 21 u32 in[MLX5_ST_SZ_DW(dealloc_sf_in)] = {}; in mlx5_cmd_dealloc_sf() 31 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {}; in mlx5_cmd_sf_enable_hca() 32 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; in mlx5_cmd_sf_enable_hca() 42 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {}; in mlx5_cmd_sf_disable_hca() 43 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; in mlx5_cmd_sf_disable_hca()
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H A D | vhca_event.c | 35 u32 in[MLX5_ST_SZ_DW(query_vhca_state_in)] = {}; in mlx5_cmd_query_vhca_state() 47 u32 out[MLX5_ST_SZ_DW(modify_vhca_state_out)] = {}; in mlx5_cmd_modify_vhca_state() 58 u32 out[MLX5_ST_SZ_DW(modify_vhca_state_out)] = {}; in mlx5_modify_vhca_sw_id() 59 u32 in[MLX5_ST_SZ_DW(modify_vhca_state_in)] = {}; in mlx5_modify_vhca_sw_id() 72 u32 in[MLX5_ST_SZ_DW(modify_vhca_state_in)] = {}; in mlx5_vhca_event_arm() 83 u32 out[MLX5_ST_SZ_DW(query_vhca_state_out)] = {}; in mlx5_vhca_event_notify()
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/linux/drivers/infiniband/hw/mlx5/ |
H A D | cmd.c | 10 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {}; in mlx5r_cmd_query_special_mkeys() 11 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {}; in mlx5r_cmd_query_special_mkeys() 48 u32 in[MLX5_ST_SZ_DW(query_cong_params_in)] = {}; in mlx5_cmd_query_cong_params() 59 u32 in[MLX5_ST_SZ_DW(destroy_tir_in)] = {}; in mlx5_cmd_destroy_tir() 69 u32 in[MLX5_ST_SZ_DW(destroy_tis_in)] = {}; in mlx5_cmd_destroy_tis() 79 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {}; in mlx5_cmd_destroy_rqt() 90 u32 in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {}; in mlx5_cmd_alloc_transport_domain() 91 u32 out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {}; in mlx5_cmd_alloc_transport_domain() 109 u32 in[MLX5_ST_SZ_DW(dealloc_transport_domain_in)] = {}; in mlx5_cmd_dealloc_transport_domain() 120 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {}; in mlx5_cmd_dealloc_pd() [all …]
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H A D | qpc.c | 198 u32 in[MLX5_ST_SZ_DW(destroy_dct_in)] = {}; in _mlx5_core_destroy_dct() 235 u32 din[MLX5_ST_SZ_DW(destroy_qp_in)] = {}; in mlx5_qpc_create_qp() 268 u32 in[MLX5_ST_SZ_DW(drain_dct_in)] = {}; in mlx5_core_drain_dct() 309 u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {}; in mlx5_core_destroy_qp() 325 u32 in[MLX5_ST_SZ_DW(set_delay_drop_params_in)] = {}; in mlx5_core_set_delay_drop() 531 u32 in[MLX5_ST_SZ_DW(query_qp_in)] = {}; in mlx5_core_qp_query() 543 u32 in[MLX5_ST_SZ_DW(query_dct_in)] = {}; in mlx5_core_dct_query() 555 u32 out[MLX5_ST_SZ_DW(alloc_xrcd_out)] = {}; in mlx5_core_xrcd_alloc() 556 u32 in[MLX5_ST_SZ_DW(alloc_xrcd_in)] = {}; in mlx5_core_xrcd_alloc() 568 u32 in[MLX5_ST_SZ_DW(dealloc_xrcd_in)] = {}; in mlx5_core_xrcd_dealloc() [all …]
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H A D | srq_cmd.c | 117 u32 create_out[MLX5_ST_SZ_DW(create_srq_out)] = {0}; in create_srq_cmd() 166 u32 in[MLX5_ST_SZ_DW(destroy_srq_in)] = {}; in destroy_srq_cmd() 178 u32 in[MLX5_ST_SZ_DW(arm_rq_in)] = {}; in arm_srq_cmd() 192 u32 in[MLX5_ST_SZ_DW(query_srq_in)] = {}; in query_srq_cmd() 220 u32 create_out[MLX5_ST_SZ_DW(create_xrc_srq_out)]; in create_xrc_srq_cmd() 273 u32 in[MLX5_ST_SZ_DW(destroy_xrc_srq_in)] = {}; in destroy_xrc_srq_cmd() 285 u32 in[MLX5_ST_SZ_DW(arm_xrc_srq_in)] = {}; in arm_xrc_srq_cmd() 301 u32 in[MLX5_ST_SZ_DW(query_xrc_srq_in)] = {}; in query_xrc_srq_cmd() 388 u32 in[MLX5_ST_SZ_DW(destroy_rmp_in)] = {}; in destroy_rmp_cmd() 478 u32 create_out[MLX5_ST_SZ_DW(create_xrq_out)] = {0}; in create_xrq_cmd() [all …]
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/linux/drivers/vdpa/mlx5/core/ |
H A D | resources.c | 12 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {}; in alloc_pd() 13 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {}; in alloc_pd() 28 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {}; in dealloc_pd() 39 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {}; in get_null_mkey() 40 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {}; in get_null_mkey() 53 u32 out[MLX5_ST_SZ_DW(create_uctx_out)] = {}; in create_uctx() 83 u32 out[MLX5_ST_SZ_DW(destroy_uctx_out)] = {}; in destroy_uctx() 84 u32 in[MLX5_ST_SZ_DW(destroy_uctx_in)] = {}; in destroy_uctx() 97 u32 out[MLX5_ST_SZ_DW(create_tis_out)] = {}; in mlx5_vdpa_create_tis() 111 u32 in[MLX5_ST_SZ_DW(destroy_tis_in)] = {}; in mlx5_vdpa_destroy_tis() [all …]
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/linux/drivers/net/ethernet/mellanox/mlx5/core/en/ |
H A D | port.c | 38 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_query_eth_autoneg() 55 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_set_eth_ptys() 56 u32 in[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_set_eth_ptys() 142 u32 in[MLX5_ST_SZ_DW(sbpr_reg)] = {}; in mlx5e_port_query_sbpr() 154 u32 out[MLX5_ST_SZ_DW(sbpr_reg)] = {}; in mlx5e_port_set_sbpr() 155 u32 in[MLX5_ST_SZ_DW(sbpr_reg)] = {}; in mlx5e_port_set_sbpr() 171 u32 in[MLX5_ST_SZ_DW(sbcm_reg)] = {}; in mlx5e_port_query_sbcm() 184 u32 out[MLX5_ST_SZ_DW(sbcm_reg)] = {}; in mlx5e_port_set_sbcm() 185 u32 in[MLX5_ST_SZ_DW(sbcm_reg)] = {}; in mlx5e_port_set_sbcm() 432 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {}; in mlx5e_fec_in_caps() [all …]
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H A D | tir.c | 12 MLX5_ST_SZ_DW(create_tir_in) > MLX5_ST_SZ_DW(modify_tir_in) ? \ 13 MLX5_ST_SZ_DW(create_tir_in) : MLX5_ST_SZ_DW(modify_tir_in) \
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H A D | monitor_stats.c | 50 u32 in[MLX5_ST_SZ_DW(arm_monitor_counter_in)] = {}; in mlx5e_monitor_counter_arm() 118 u32 in[MLX5_ST_SZ_DW(set_monitor_counter_in)] = {}; in mlx5e_set_monitor_counter() 157 u32 in[MLX5_ST_SZ_DW(set_monitor_counter_in)] = {}; in mlx5e_monitor_counter_cleanup()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/ |
H A D | geneve.c | 22 u32 in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {}; in mlx5_geneve_tlv_option_create() 23 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; in mlx5_geneve_tlv_option_create() 53 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; in mlx5_geneve_tlv_option_destroy() 54 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {}; in mlx5_geneve_tlv_option_destroy()
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H A D | crypto.c | 138 u32 in[MLX5_ST_SZ_DW(sync_crypto_in)] = {}; in mlx5_crypto_cmd_sync_crypto() 161 u32 in[MLX5_ST_SZ_DW(create_encryption_key_in)] = {}; in mlx5_crypto_create_dek_bulk() 162 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; in mlx5_crypto_create_dek_bulk() 192 u32 in[MLX5_ST_SZ_DW(modify_encryption_key_in)] = {}; in mlx5_crypto_modify_dek_key() 193 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; in mlx5_crypto_modify_dek_key() 227 u32 in[MLX5_ST_SZ_DW(create_encryption_key_in)] = {}; in mlx5_crypto_create_dek_key() 228 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; in mlx5_crypto_create_dek_key() 263 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {}; in mlx5_crypto_destroy_dek_key() 264 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; in mlx5_crypto_destroy_dek_key()
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H A D | port_tun.c | 18 u32 out[MLX5_ST_SZ_DW(pcmr_reg)]; in mlx5_query_port_tun_entropy() 44 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0}; in mlx5_set_port_tun_entropy_calc() 59 u32 in[MLX5_ST_SZ_DW(pcmr_reg)] = {0}; in mlx5_set_port_gre_tun_entropy_calc()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/diag/ |
H A D | fw_tracer.c | 42 u32 out[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_query_mtrc_caps() 43 u32 in[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_query_mtrc_caps() 86 u32 in[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_set_mtrc_caps_trace_owner() 97 u32 out[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_fw_tracer_ownership_acquire() 118 u32 out[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_fw_tracer_ownership_release() 270 u32 in[MLX5_ST_SZ_DW(mtrc_cap)] = {0}; in mlx5_tracer_read_strings_db() 345 u32 out[MLX5_ST_SZ_DW(mtrc_ctrl)] = {0}; in mlx5_fw_tracer_arm() 346 u32 in[MLX5_ST_SZ_DW(mtrc_ctrl)] = {0}; in mlx5_fw_tracer_arm() 773 u32 out[MLX5_ST_SZ_DW(mtrc_conf)] = {0}; in mlx5_fw_tracer_set_mtrc_conf() 774 u32 in[MLX5_ST_SZ_DW(mtrc_conf)] = {0}; in mlx5_fw_tracer_set_mtrc_conf() [all …]
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/linux/drivers/vfio/pci/mlx5/ |
H A D | cmd.c | 41 u32 out[MLX5_ST_SZ_DW(suspend_vhca_out)] = {}; in mlx5vf_cmd_suspend_vhca() 42 u32 in[MLX5_ST_SZ_DW(suspend_vhca_in)] = {}; in mlx5vf_cmd_suspend_vhca() 74 u32 out[MLX5_ST_SZ_DW(resume_vhca_out)] = {}; in mlx5vf_cmd_resume_vhca() 75 u32 in[MLX5_ST_SZ_DW(resume_vhca_in)] = {}; in mlx5vf_cmd_resume_vhca() 92 u32 out[MLX5_ST_SZ_DW(query_vhca_migration_state_out)] = {}; in mlx5vf_cmd_query_vhca_migration_state() 93 u32 in[MLX5_ST_SZ_DW(query_vhca_migration_state_in)] = {}; in mlx5vf_cmd_query_vhca_migration_state() 287 u32 in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {}; in mlx5vf_cmd_get_vhca_id() 689 u32 in[MLX5_ST_SZ_DW(save_vhca_state_in)] = {}; in mlx5vf_cmd_save_vhca_state() 778 u32 out[MLX5_ST_SZ_DW(load_vhca_state_out)] = {}; in mlx5vf_cmd_load_vhca_state() 779 u32 in[MLX5_ST_SZ_DW(load_vhca_state_in)] = {}; in mlx5vf_cmd_load_vhca_state() [all …]
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/linux/drivers/net/ethernet/mellanox/mlx5/core/ipoib/ |
H A D | ipoib.c | 207 u32 in[MLX5_ST_SZ_DW(rst2init_qp_in)] = {}; in mlx5i_init_underlay_qp() 225 u32 in[MLX5_ST_SZ_DW(init2rtr_qp_in)] = {}; in mlx5i_init_underlay_qp() 234 u32 in[MLX5_ST_SZ_DW(rtr2rts_qp_in)] = {}; in mlx5i_init_underlay_qp() 246 u32 in[MLX5_ST_SZ_DW(qp_2err_in)] = {}; in mlx5i_init_underlay_qp() 259 u32 in[MLX5_ST_SZ_DW(qp_2rst_in)] = {}; in mlx5i_uninit_underlay_qp() 271 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {}; in mlx5i_create_underlay_qp() 272 u32 in[MLX5_ST_SZ_DW(create_qp_in)] = {}; in mlx5i_create_underlay_qp() 307 u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {}; in mlx5i_destroy_underlay_qp() 321 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {}; in mlx5i_create_tis()
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