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Searched refs:MLX5_CAP_GEN (Results 1 – 25 of 75) sorted by relevance

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/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dsf.h11 return MLX5_CAP_GEN(dev, sf_base_id); in mlx5_sf_start_function_id()
18 return MLX5_CAP_GEN(dev, sf); in mlx5_sf_supported()
25 if (MLX5_CAP_GEN(dev, max_num_sf)) in mlx5_sf_max_functions()
26 return MLX5_CAP_GEN(dev, max_num_sf); in mlx5_sf_max_functions()
28 return 1 << MLX5_CAP_GEN(dev, log_max_sf); in mlx5_sf_max_functions()
H A Dsd.c184 return (u32)((MLX5_CAP_GEN(dev, native_port_num) << 8) | sd_group); in mlx5_sd_group_id()
194 if (!MLX5_CAP_GEN(dev, eswitch_manager)) in mlx5_sd_caps_supported()
196 if (!MLX5_CAP_GEN(dev, silent_mode_set) && in mlx5_sd_caps_supported()
197 !MLX5_CAP_GEN(dev, silent_mode_query)) in mlx5_sd_caps_supported()
201 if (!MLX5_CAP_GEN(dev, cross_vhca_rqt)) in mlx5_sd_caps_supported()
554 if (MLX5_CAP_GEN(dev, silent_mode_query)) { in sd_register()
648 u16 vhca_id_to_be_accessed = MLX5_CAP_GEN(primary, vhca_id); in sd_secondary_create_alias_ft()
751 MLX5_CAP_GEN(primary, vhca_id)); in sd_print_group()
755 MLX5_CAP_GEN(pos, vhca_id)); in sd_print_group()
767 MLX5_CAP_GEN(dev, vhca_id)); in dev_read()
H A Dgid.c130 if (MLX5_CAP_GEN(dev, port_type) != MLX5_CAP_PORT_TYPE_ETH) in mlx5_core_roce_gid_set()
145 if (MLX5_CAP_GEN(dev, num_vhca_ports) > 0) in mlx5_core_roce_gid_set()
/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Dfw.c150 if (MLX5_CAP_GEN(dev, port_selection_cap)) { in mlx5_query_hca_caps()
156 if (MLX5_CAP_GEN(dev, hca_cap_2)) { in mlx5_query_hca_caps()
162 if (MLX5_CAP_GEN(dev, eth_net_offloads)) { in mlx5_query_hca_caps()
169 if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { in mlx5_query_hca_caps()
176 if (MLX5_CAP_GEN(dev, pg)) { in mlx5_query_hca_caps()
182 if (MLX5_CAP_GEN(dev, atomic)) { in mlx5_query_hca_caps()
188 if (MLX5_CAP_GEN(dev, roce)) { in mlx5_query_hca_caps()
194 if (MLX5_CAP_GEN(dev, nic_flow_table) || in mlx5_query_hca_caps()
195 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) { in mlx5_query_hca_caps()
212 if (MLX5_CAP_GEN(dev, qos)) { in mlx5_query_hca_caps()
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H A Den_dcbnl.c75 #define MLX5_DSCP_SUPPORTED(mdev) (MLX5_CAP_GEN(mdev, qcam_reg) && \
107 if (!MLX5_CAP_GEN(priv->mdev, dcbx)) in mlx5e_dcbnl_switch_to_host_mode()
132 if (!MLX5_CAP_GEN(priv->mdev, ets)) in mlx5e_dcbnl_ieee_getets()
358 if (!MLX5_CAP_GEN(priv->mdev, ets)) in mlx5e_dcbnl_ieee_setets()
462 if ((!mode) && MLX5_CAP_GEN(priv->mdev, dcbx)) { in mlx5e_dcbnl_setdcbx()
494 if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager) || in mlx5e_dcbnl_ieee_setapp()
547 if (!MLX5_CAP_GEN(priv->mdev, vport_group_manager) || in mlx5e_dcbnl_ieee_delapp()
676 if (!MLX5_CAP_GEN(mdev, ets)) in mlx5e_dcbnl_setall()
785 if (!MLX5_CAP_GEN(priv->mdev, ets)) { in mlx5e_dcbnl_getpgtccfgtx()
1072 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos)) in mlx5e_dcbnl_build_netdev()
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H A Den_common.c43 bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write); in mlx5e_mkey_set_relaxed_ordering()
44 bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read) || in mlx5e_mkey_set_relaxed_ordering()
46 MLX5_CAP_GEN(mdev, relaxed_ordering_read_pci_enabled)); in mlx5e_mkey_set_relaxed_ordering()
106 return MLX5_CAP_GEN(mdev, lag_tx_port_affinity) && mlx5e_get_num_lag_ports(mdev) > 1; in mlx5_lag_should_assign_affinity()
285 if (MLX5_CAP_GEN(mdev, tis_tir_td_order)) in mlx5e_refresh_tirs()
H A Duar.c63 if (MLX5_CAP_GEN(mdev, uar_4k)) in uars_per_sys_page()
64 return MLX5_CAP_GEN(mdev, num_of_uars_per_page); in uars_per_sys_page()
73 if (MLX5_CAP_GEN(mdev, uar_4k)) in uar2pfn()
201 (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) + MLX5_BF_OFFSET; in map_offset()
281 bf_reg_size = 1 << MLX5_CAP_GEN(dev, log_bf_reg_size); in addr_to_dbi_in_syspage()
H A Den_ethtool.c625 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) { in mlx5e_ethtool_get_coalesce()
662 if (!MLX5_CAP_GEN(priv->mdev, cq_moderation)) in mlx5e_ethtool_get_per_queue_coalesce()
773 if (!MLX5_CAP_GEN(mdev, cq_moderation) || in mlx5e_ethtool_set_coalesce()
774 !MLX5_CAP_GEN(mdev, cq_period_mode_modify)) { in mlx5e_ethtool_set_coalesce()
800 !MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe)) { in mlx5e_ethtool_set_coalesce()
893 if (!MLX5_CAP_GEN(mdev, cq_moderation)) in mlx5e_ethtool_set_per_queue_coalesce()
1745 if (!MLX5_CAP_GEN(mdev, vport_group_manager)) in mlx5e_ethtool_set_pauseparam()
1777 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz) || in mlx5e_ethtool_get_ts_info()
1807 if (MLX5_CAP_GEN(mdev, wol_g)) in mlx5e_get_wol_supported()
1810 if (MLX5_CAP_GEN(mdev, wol_s)) in mlx5e_get_wol_supported()
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H A Dmain.c165 if (!MLX5_CAP_GEN(dev, driver_version)) in mlx5_set_driver_version()
372 if (!MLX5_CAP_GEN(dev, atomic)) in handle_hca_cap_atomic()
402 !MLX5_CAP_GEN(dev, pg)) in handle_hca_cap_odp()
486 return MLX5_CAP_GEN(dev, roce); in mlx5_is_roce_on()
542 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)), in handle_hca_cap()
611 if (MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce)) in handle_hca_cap()
646 return (MLX5_CAP_GEN(dev, roce_rw_supported) && !mlx5_is_roce_on(dev)) || in is_roce_fw_disabled()
647 (!MLX5_CAP_GEN(dev, roce_rw_supported) && !MLX5_CAP_GEN(dev, roce)); in is_roce_fw_disabled()
684 if (!MLX5_CAP_GEN(dev, port_selection_cap)) in handle_hca_cap_port_selection()
783 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH) in mlx5_core_set_hca_defaults()
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H A Dwc.c126 if (MLX5_CAP_GEN(mdev, cqe_128_always) && cache_line_size() >= 128) in mlx5_wc_create_cq()
288 int buf_size = (1 << MLX5_CAP_GEN(sq->cq.mdev, log_bf_reg_size)) / 2; in mlx5_wc_post_nop()
414 if (!MLX5_CAP_GEN(mdev, bf)) { in mlx5_wc_support_get()
419 if (!MLX5_CAP_GEN(mdev, log_max_sq)) { in mlx5_wc_support_get()
H A Dmlx5_core.h389 #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \
390 MLX5_CAP_GEN((mdev), pps_modify) && \
517 if (MLX5_CAP_GEN(dev, max_num_eqs)) in mlx5_max_eq_cap_get()
518 return MLX5_CAP_GEN(dev, max_num_eqs); in mlx5_max_eq_cap_get()
520 return 1 << MLX5_CAP_GEN(dev, log_max_eq); in mlx5_max_eq_cap_get()
H A Ddevlink.c469 if (new_state && !MLX5_CAP_GEN(dev, roce) && in mlx5_devlink_enable_roce_validate()
470 !(MLX5_CAP_GEN(dev, roce_rw_supported) && MLX5_CAP_GEN_MAX(dev, roce))) { in mlx5_devlink_enable_roce_validate()
527 if (val32 > BIT(MLX5_CAP_GEN(dev, log_max_hairpin_num_packets))) { in mlx5_devlink_hairpin_queue_size_validate()
530 BIT(MLX5_CAP_GEN(dev, log_max_hairpin_num_packets))); in mlx5_devlink_hairpin_queue_size_validate()
575 MLX5_CAP_GEN(dev, log_max_hairpin_num_packets))); in mlx5_devlink_hairpin_params_init_values()
601 value.vbool = MLX5_CAP_GEN(dev, roce) && !mlx5_dev_is_lightweight(dev); in mlx5_devlink_set_params_init_values()
937 value.vu32 = 1 << MLX5_CAP_GEN(dev, log_max_current_uc_list); in mlx5_devlink_max_uc_list_params_register()
H A Dfs_counters.c68 (1 << MLX5_CAP_GEN(dev, log_max_flow_counter_bulk))); in get_init_bulk_query_len()
74 (1 << MLX5_CAP_GEN(dev, log_max_flow_counter_bulk))); in get_max_bulk_query_len()
268 if (aging && MLX5_CAP_GEN(dev, flow_counter_bulk_alloc) != 0) { in mlx5_fc_acquire()
460 alloc_bitmask = MLX5_CAP_GEN(dev, flow_counter_bulk_alloc); in mlx5_fc_bulk_create()
/linux/drivers/net/ethernet/mellanox/mlx5/core/en/
H A Dmonitor_stats.c25 if (!MLX5_CAP_GEN(mdev, max_num_of_monitor_counters)) in mlx5e_monitor_counter_cap()
28 MLX5_CAP_GEN(mdev, num_ppcnt_monitor_counters) < in mlx5e_monitor_counter_cap()
31 if (MLX5_CAP_GEN(mdev, num_q_monitor_counters) < in mlx5e_monitor_counter_cap()
114 int max_num_of_counters = MLX5_CAP_GEN(mdev, max_num_of_monitor_counters); in mlx5e_set_monitor_counter()
115 int num_q_counters = MLX5_CAP_GEN(mdev, num_q_monitor_counters); in mlx5e_set_monitor_counter()
117 MLX5_CAP_GEN(mdev, num_ppcnt_monitor_counters); in mlx5e_set_monitor_counter()
H A Dchannels.c34 *vhca_id = MLX5_CAP_GEN(c->mdev, vhca_id); in mlx5e_channels_get_regular_rqn()
46 *vhca_id = MLX5_CAP_GEN(c->mdev, vhca_id); in mlx5e_channels_get_xsk_rqn()
H A Dtc_tun_geneve.c12 return !!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) & MLX5_FLEX_PROTO_GENEVE); in mlx5e_tc_tun_can_offload_geneve()
160 u8 max_tlv_option_data_len = MLX5_CAP_GEN(priv->mdev, max_geneve_tlv_option_data_len); in mlx5e_tc_tun_parse_geneve_options()
161 u8 max_tlv_options = MLX5_CAP_GEN(priv->mdev, max_geneve_tlv_options); in mlx5e_tc_tun_parse_geneve_options()
H A Dport_buffer.h42 #define MLX5_BUFFER_SUPPORTED(mdev) (MLX5_CAP_GEN(mdev, pcam_reg) && \
/linux/drivers/net/ethernet/mellanox/mlx5/core/en_accel/
H A Dktls.h26 if (!MLX5_CAP_GEN(mdev, tls_tx) && !MLX5_CAP_GEN(mdev, tls_rx)) in mlx5e_is_ktls_device()
29 if (!MLX5_CAP_GEN(mdev, log_max_dek)) in mlx5e_is_ktls_device()
65 return !is_kdump_kernel() && MLX5_CAP_GEN(mdev, tls_tx) && in mlx5e_is_ktls_tx()
/linux/drivers/net/ethernet/mellanox/mlx5/core/esw/acl/
H A Degress_ofld.c77 if (MLX5_CAP_GEN(esw->dev, prio_tag_required)) { in esw_acl_egress_ofld_rules_create()
125 if (MLX5_CAP_GEN(esw->dev, prio_tag_required)) in esw_acl_egress_ofld_fwd_grp_create()
186 if (!MLX5_CAP_GEN(esw->dev, prio_tag_required)) in esw_acl_egress_ofld_setup()
284 fwd_dest.vport.vhca_id = MLX5_CAP_GEN(esw->dev, vhca_id); in mlx5_esw_acl_egress_vport_bond()
/linux/include/linux/mlx5/
H A Ddriver.h1242 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager); in mlx5_core_is_ecpf_esw_manager()
1262 return MLX5_CAP_GEN(dev, vport_group_manager) && in mlx5_lag_is_lacp_owner()
1263 (MLX5_CAP_GEN(dev, num_lag_ports) > 1) && in mlx5_lag_is_lacp_owner()
1264 MLX5_CAP_GEN(dev, lag_master); in mlx5_lag_is_lacp_owner()
1289 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && in mlx5_core_is_mp_slave()
1309 return MLX5_CAP_GEN(dev, native_port_num); in mlx5_core_native_port_num()
1314 int idx = MLX5_CAP_GEN(dev, native_port_num); in mlx5_get_dev_index()
1330 if (MLX5_CAP_GEN(dev, roce_rw_supported)) in mlx5_get_roce_state()
1331 return MLX5_CAP_GEN(dev, roce); in mlx5_get_roce_state()
1346 if (!MLX5_CAP_GEN(mdev, log_max_dek)) in mlx5e_is_macsec_device()
/linux/drivers/infiniband/hw/mlx5/
H A Dcmd.c15 is_terminate = MLX5_CAP_GEN(dev->mdev, terminate_scatter_list_mkey); in mlx5r_cmd_query_special_mkeys()
16 is_dump = MLX5_CAP_GEN(dev->mdev, dump_fill_mkey); in mlx5r_cmd_query_special_mkeys()
17 is_null = MLX5_CAP_GEN(dev->mdev, null_mkey); in mlx5r_cmd_query_special_mkeys()
259 MLX5_SET(query_vuid_in, in, vhca_id, MLX5_CAP_GEN(dev, vhca_id)); in mlx5_cmd_query_vuid()
/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/
H A Dmlx5dr.h157 return MLX5_CAP_GEN(dev, roce) && in mlx5dr_is_supported()
160 (MLX5_CAP_GEN(dev, steering_format_version) <= in mlx5dr_is_supported()
/linux/drivers/net/ethernet/mellanox/mlx5/core/sf/dev/
H A Ddev.c34 return MLX5_CAP_GEN(dev, sf) && mlx5_vhca_event_supported(dev); in mlx5_sf_dev_supported()
300 if (MLX5_CAP_GEN(table->dev, eswitch_manager)) in mlx5_sf_dev_create_active_works()
346 table->sf_bar_length = 1 << (MLX5_CAP_GEN(dev, log_min_sf_size) + 12); in mlx5_sf_dev_table_create()
/linux/drivers/net/ethernet/mellanox/mlx5/core/esw/
H A Dlegacy.c404 if (!MLX5_CAP_GEN(dev, receive_discard_vport_down) && in mlx5_esw_query_vport_drop_stats()
405 !MLX5_CAP_GEN(dev, transmit_discard_vport_down)) in mlx5_esw_query_vport_drop_stats()
414 if (MLX5_CAP_GEN(dev, receive_discard_vport_down)) in mlx5_esw_query_vport_drop_stats()
416 if (MLX5_CAP_GEN(dev, transmit_discard_vport_down)) in mlx5_esw_query_vport_drop_stats()
/linux/drivers/net/ethernet/mellanox/mlx5/core/en/tc/act/
H A Dsample.c33 if (MLX5_CAP_GEN(mdev, reg_c_preserve) || in mlx5e_tc_act_sample_is_multi_table()

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