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Searched refs:MLX5_CAP_ETH (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dvxlan.h42 return MLX5_CAP_ETH(mdev, max_vxlan_udp_ports) ?: 4; in mlx5_vxlan_max_udp_ports()
H A Dvxlan.c151 if (!MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || !mlx5_core_is_pf(mdev)) in mlx5_vxlan_create()
H A Dfs_ttc.c201 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre); in mlx5_tunnel_proto_supported_rx()
204 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) || in mlx5_tunnel_proto_supported_rx()
205 MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_rx)); in mlx5_tunnel_proto_supported_rx()
/linux/drivers/net/ethernet/mellanox/mlx5/core/en/
H A Dtc_tun_mplsoudp.c66 if (!MLX5_CAP_ETH(priv->mdev, tunnel_stateless_mpls_over_udp) && in parse_tunnel()
H A Dparams.c1098 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout) in mlx5e_choose_lro_timeout()
1101 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]); in mlx5e_choose_lro_timeout()
1211 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(mdev, reg_umr_sq)); in mlx5e_build_icosq_param()
1227 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(mdev, reg_umr_sq)); in mlx5e_build_async_icosq_param()
H A Dtxrx.h493 if (!MLX5_CAP_ETH(mdev, swp_csum_l4_partial) || !skb_is_gso(skb)) in mlx5e_swp_encap_csum_partial()
H A Dptp.c342 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert)) in mlx5e_ptp_alloc_txqsq()
/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A Den.h1128 return MLX5_CAP_ETH(mdev, swp) && in mlx5_tx_swp_supported()
1129 MLX5_CAP_ETH(mdev, swp_csum) && MLX5_CAP_ETH(mdev, swp_lso); in mlx5_tx_swp_supported()
1205 MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe); in mlx5e_tx_mpwqe_supported()
H A Den_main.c106 MLX5_CAP_ETH(mdev, reg_umr_sq); in mlx5e_check_fragmented_striding_rq_cap()
1309 if (MLX5_CAP_ETH(mdev, cqe_checksum_full)) in mlx5e_open_rq()
1630 if (!MLX5_CAP_ETH(mdev, wqe_vlan_insert)) in mlx5e_alloc_txqsq()
1696 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) in mlx5e_create_sq()
4888 return MLX5_CAP_ETH(mdev, tunnel_stateless_gre); in mlx5e_tunnel_proto_supported_tx()
4891 return (MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip) || in mlx5e_tunnel_proto_supported_tx()
4892 MLX5_CAP_ETH(mdev, tunnel_stateless_ip_over_ip_tx)); in mlx5e_tunnel_proto_supported_tx()
4908 return MLX5_CAP_ETH(mdev, tunnel_stateless_mpls_over_gre); in mlx5e_gre_tunnel_inner_proto_offload_supported()
5512 if (!!MLX5_CAP_ETH(mdev, lro_cap) && in mlx5e_build_nic_netdev()
5513 !MLX5_CAP_ETH(mdev, tunnel_lro_vxlan) && in mlx5e_build_nic_netdev()
[all …]
H A Dvport.c110 switch (MLX5_CAP_ETH(mdev, wqe_inline_mode)) { in mlx5_query_min_inline()
H A Deswitch_offloads.c2204 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) { in mlx5_eswitch_inline_mode_get()
3882 switch (MLX5_CAP_ETH(dev, wqe_inline_mode)) { in mlx5_devlink_eswitch_inline_mode_set()
/linux/drivers/infiniband/hw/mlx5/
H A Dmain.c949 if (MLX5_CAP_ETH(mdev, csum_cap)) { in mlx5_ib_query_device()
955 if (MLX5_CAP_ETH(dev->mdev, vlan_cap)) in mlx5_ib_query_device()
960 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); in mlx5_ib_query_device()
1006 MLX5_CAP_ETH(dev->mdev, scatter_fcs) && in mlx5_ib_query_device()
1163 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe)) in mlx5_ib_query_device()
1167 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe)) in mlx5_ib_query_device()
1201 if (MLX5_CAP_ETH(mdev, swp)) { in mlx5_ib_query_device()
1205 if (MLX5_CAP_ETH(mdev, swp_csum)) in mlx5_ib_query_device()
1209 if (MLX5_CAP_ETH(mdev, swp_lso)) in mlx5_ib_query_device()
1244 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan)) in mlx5_ib_query_device()
[all …]
H A Dqp.c1380 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe)) in create_raw_packet_qp_sq()
1389 MLX5_CAP_ETH(dev->mdev, swp)) in create_raw_packet_qp_sq()
2939 cond = MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan) || in process_vendor_flags()
2940 MLX5_CAP_ETH(mdev, tunnel_stateless_gre) || in process_vendor_flags()
2941 MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx); in process_vendor_flags()
3033 MLX5_CAP_ETH(mdev, scatter_fcs); in process_create_flags()
3038 MLX5_CAP_ETH(mdev, vlan_cap); in process_create_flags()
5301 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) { in create_rq()
5310 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) { in create_rq()
5667 MLX5_CAP_ETH(dev->mdev, vlan_cap))) { in mlx5_ib_modify_wq()
/linux/drivers/net/ethernet/mellanox/mlx5/core/en_accel/
H A Dipsec_offload.c40 MLX5_CAP_ETH(mdev, insert_trailer) && MLX5_CAP_ETH(mdev, swp)) in mlx5_ipsec_device_caps()
H A Dipsec.c1222 if (!MLX5_CAP_ETH(mdev, swp_csum)) { in mlx5e_ipsec_build_netdev()
1230 if (!MLX5_CAP_ETH(mdev, swp_lso)) { in mlx5e_ipsec_build_netdev()