Home
last modified time | relevance | path

Searched refs:MI_FLUSH_DW_USE_GTT (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c205 *cs++ = HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; in mi_flush_dw()
381 *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; in gen6_emit_breadcrumb_xcs()
402 *cs++ = I915_GEM_HWS_SEQNO_ADDR | MI_FLUSH_DW_USE_GTT; in gen7_emit_breadcrumb_xcs()
H A Dgen8_engine_cs.h138 gtt_offset | MI_FLUSH_DW_USE_GTT, in gen8_emit_ggtt_write()
H A Dintel_gpu_commands.h174 #define MI_FLUSH_DW_USE_GTT (1<<2) macro
/linux/drivers/gpu/drm/xe/instructions/
H A Dxe_mi_commands.h58 #define MI_FLUSH_DW_USE_GTT REG_BIT(2) macro
/linux/drivers/gpu/drm/xe/
H A Dxe_ring_ops.c98 dw[i++] = addr | MI_FLUSH_DW_USE_GTT; in emit_flush_imm_ggtt()
121 dw[i++] = LRC_PPHWSP_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; in emit_flush_invalidate()
420 dw[i++] = xe_lrc_seqno_ggtt_addr(lrc) | MI_FLUSH_DW_USE_GTT; in emit_migration_job_gen12()
/linux/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp_cmd.c40 *cs++ = I915_GEM_HWS_PXP_ADDR | MI_FLUSH_DW_USE_GTT; in pxp_emit_session_selection()
/linux/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c354 .mask = MI_FLUSH_DW_USE_GTT,
398 .mask = MI_FLUSH_DW_USE_GTT,
435 .mask = MI_FLUSH_DW_USE_GTT,